Selective Oxidation Of Ion-amorphousized Layer Patents (Class 438/966)
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Patent number: 8021989Abstract: One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.Type: GrantFiled: May 26, 2006Date of Patent: September 20, 2011Assignee: IMECInventors: Staf Verhaegen, Axel Nackaerts
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Patent number: 7538395Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.Type: GrantFiled: September 21, 2007Date of Patent: May 26, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Thomas Keena, Ki Chang, Francine Y. Robb, Mingjiao Liu, Ali Salih, John Michael Parsey, Jr., George Chang
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Patent number: 7425480Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.Type: GrantFiled: April 23, 2007Date of Patent: September 16, 2008Assignee: Kabushiki Kaisha TohisbaInventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
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Patent number: 7303946Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.Type: GrantFiled: April 27, 2000Date of Patent: December 4, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
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Patent number: 6998353Abstract: The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300° C. to 600° C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50° C. to 150° C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate.Type: GrantFiled: November 5, 2001Date of Patent: February 14, 2006Assignee: Ibis Technology CorporationInventors: Yuri Erokhin, Julian G. Blake
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Patent number: 6900111Abstract: A method for forming a reliable and ultra-thin oxide layer, such as a gate oxide layer of an MOS transistor, comprises an annealing step immediately performed prior to oxidizing a substrate. The annealing step is performed in an inert gas ambient to avoid oxidation of the semiconductor surface prior to achieving a required low oxidizing temperature. Preferably, the annealing step and the oxidizing step are carried out as an in situ process, thereby minimizing the thermal budget of the overall process.Type: GrantFiled: April 19, 2002Date of Patent: May 31, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Stephan Krügel, Falk Graetsch
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Patent number: 6869891Abstract: A method for forming a plurality of grooves of a semiconductor device having of a plurality of MOS transistors is provided. A plurality of photoresist patterns are formed on a semiconductor substrate. Ions are implanted on a portion of the semiconductor substrate using the plurality of photoresist patterns as a mask. The plurality of photoresist patterns are removed. An oxide layer is formed on the semiconductor substrate having the implanted ions by thermal oxidation. The plurality of grooves are formed on the semiconductor substrate by removing the oxide layer.Type: GrantFiled: April 22, 2002Date of Patent: March 22, 2005Assignee: Samsung Electronics, Co., LTDInventor: Nak-jin Son
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Patent number: 6855994Abstract: A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.Type: GrantFiled: November 29, 1999Date of Patent: February 15, 2005Assignee: The Regents of the University of CaliforniaInventors: Ya-Chin King, Tsu-Jae King, Chen Ming Hu
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Patent number: 6743651Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i.e., heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.Type: GrantFiled: April 23, 2002Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Jack O. Chu, Feng-Yi Huang, Steven J. Koester, Devendra K. Sadana
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Patent number: 6455405Abstract: A method for forming dual thickness gate oxide layers comprising the following steps. A structure having at least a first area and a second area is provided. The second area of the structure is masked. Ion implanting Si4+ or Ge4+ ions into the unmasked first area of the structure to form an amorphous layer within the first area of the structure. The second area of the structure is unmasked. The first and second areas of the structure are oxidized to form: a first gate oxide layer upon the structure within the first area; and a second gate oxide layer upon the structure within the second area. The first gate oxide layer having a greater thickness than the second gate oxide layer, completing formation of the dual thickness gate oxide layers.Type: GrantFiled: January 23, 2002Date of Patent: September 24, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Shao-Yen Ku
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Patent number: 6407014Abstract: The invention provides a method for the production of high quality thermally grown oxide on top of silicon carbide. The high quality oxide is obtained by selectively removing the carbon from the silicon carbide in the areas where oxide formation is desired or required.Type: GrantFiled: December 16, 1999Date of Patent: June 18, 2002Assignee: Philips Electronics North America CorporationInventor: Dev Alok
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Patent number: 6383859Abstract: A silicon film is formed on a semiconductor substrate, and a silicon oxide film and a polycrystalline silicon film are formed thereon. Patterning is performed for the polycrystalline silicon film to form a capacitive upper electrode. Then, patterning is performed for the silicon oxide film to form a capacitive dielectric film below the capacitive upper electrode, the capacitive dielectric film having a shape larger than that of the capacitive upper electrode. Subsequently, an anti-reflection coating film (silicon nitride film which is silicon-rich) is formed on a full surface. Then, patterning is performed for the silicon film by means of photolithography to form a capacitive lower electrode and a gate electrode of a transistor.Type: GrantFiled: December 27, 1999Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventor: Akiyoshi Watanabe
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Publication number: 20020016046Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.Type: ApplicationFiled: June 19, 2001Publication date: February 7, 2002Inventors: Robert Dolan, Bernhard Cordts, Marvin Farley, Geoffrey Ryding
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Patent number: 6232206Abstract: A method is provided for selective oxidation on source/drain regions of transistors on an integrated circuit. The method includes the steps of a) incorporating a neutral species into first kind of the source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of the source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.Type: GrantFiled: December 10, 1998Date of Patent: May 15, 2001Assignee: National Science CouncilInventors: Tiao-Yuan Huang, Horng-Chih Lin
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Patent number: 6143624Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.Type: GrantFiled: October 14, 1998Date of Patent: November 7, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
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Patent number: 6013557Abstract: A method for forming field isolation regions in multilayer semiconductor devices comprises the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.Type: GrantFiled: August 19, 1998Date of Patent: January 11, 2000Assignee: Micron Technology, Inc.Inventors: Zhiqiang Jeff Wu, Li Li
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Patent number: 5930658Abstract: A method of manufacturing a semiconductor device to negate the effects on the device performance caused by defects on the silicon substrate. An oxygen doped amorphous silicon layer is deposited onto the gate region of the semiconductor device and can have a thickness of less than 5 nanometers. The amorphous silicon provides a conformal layer over the defects on the silicon substrate. The oxygen doping of the amorphous silicon maintains the conformality of the amorphous silicon layer during subsequent processing by preventing the formation of large amorphous silicon grains during a crystallization process. The resulting silicon oxide layer has increased uniformity and can have a thickness of less than 10 nanometers.Type: GrantFiled: November 26, 1996Date of Patent: July 27, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Effiong E. Ibok
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Patent number: 5895252Abstract: A method of forming a field oxide isolation region is described, in which a masking layer is formed over a silicon substrate. The masking layer is patterned to form an opening for the field oxide isolation region, whereby the remainder of the masking layer forms an implant mask. A conductivity-imparting dopant is implanted through the opening into the silicon substrate. Oxygen is implanted through the opening into the silicon substrate in multiple implantation steps. The implant mask is removed. The field oxide isolation region is formed in and on the silicon substrate, by annealing in a non-oxygen ambient. Alternately, the field oxide isolation region is formed by annealing in oxygen, simultaneously forming a gate oxide in the region between the field oxide isolation regions.Type: GrantFiled: November 2, 1995Date of Patent: April 20, 1999Assignee: United Microelectronics CorporationInventors: Water Lur, Cheng Han Huang
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Patent number: 5780347Abstract: A method and apparatus of forming local interconnects in a MOS process deposits a layer of polysilicon over an entire region after several conventional MOS processing steps. The region is then masked to provide protected regions and unprotected regions. The mask may be used to define local interconnects and other conductive elements such as the source and drain contact regions for a MOS transistor. After masking, the region is bombarded with atoms to enhance the oxidation potential of the unprotected regions. The masking is removed and the substrate is then exposed to oxidizing conditions which cause the unprotected regions to rapidly oxidize to form a thick oxide layer. The formerly protected polysilicon regions may then be doped to render them conductive.Type: GrantFiled: May 20, 1996Date of Patent: July 14, 1998Inventor: Ashok K. Kapoor