Abstract: By using a rare earth metal having a minimal content of impurity metal element, machining it into a member and cleaning with an organic acid-base capping agent, there is obtained a rare earth metal member composed entirely of a rare earth metal and containing not more than 100 ppm of impurity metal element in a sub-surface zone, which member is characterized by a high surface purity, a large grain size, minimized grain boundaries, and improved halogen resistance or corrosion resistance.
Abstract: Techniques for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices. In one implementation, a carrier wafer is fabricated to include a membrane on one side of the carrier wafer. The membrane on the carrier wafer is then bond to a surface of a different, device wafer by a plurality of joints. Next, the carrier wafer is etched away by a dry etching chemical to expose the membrane and to leave said membrane on the device wafer. Transfer of membranes with a wet etching process is also described.
Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.
Type:
Grant
Filed:
August 27, 2002
Date of Patent:
October 18, 2005
Assignee:
Honeywell International Inc.
Inventors:
Harry Rosenberg, Bahri Ozturk, Guangxin Wang, Wesley LaRue
Abstract: Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.
Type:
Grant
Filed:
August 18, 1999
Date of Patent:
May 21, 2002
Assignee:
Fujitsu Limited, Inc.
Inventors:
Lei Zhang, Solomon Beilin, Som S. Swamy, James J. Roman
Abstract: An improved method of forming a metallization layer in a layer stack is disclosed. In one aspect of the invention, a method of performing a lithographic damascene etch on a layer stack to form a metal line is disclosed. The layer stack, which is disposed above a substrate, is comprised of an underlying layer. The method of performing the lithographic damascene etch comprises the steps of depositing a photoresist layer above the layer stack and forming a trench in the photoresist layer so that the trench is positioned over the underlying layer of the layer stack. The method continues with depositing a metal layer over the top surface of the photoresist layer and filling the trench, planarizing the metal layer down to about a level of the top surface of the photoresist layer to define a top surface of a metal line, and removing the photoresist layer to leave gaps around the metal line.
Abstract: The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.
Type:
Grant
Filed:
April 8, 1996
Date of Patent:
October 13, 1998
Assignee:
Vanguard International Semiconductor
Inventors:
JanMye Sung, Howard C. Kirsch, Chih-Yuan Lu