Of Peripheral Device Patents (Class 703/24)
  • Patent number: 11941336
    Abstract: Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 26, 2024
    Assignee: OPPSTAR TECHNOLOGY SDN BHD
    Inventors: Kim Pin Tan, Hun Wah Cheah
  • Patent number: 11914514
    Abstract: A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Martin John Robinson, Mark Landers
  • Patent number: 11886356
    Abstract: Enhanced apparatuses, systems, and techniques for coupling network-linked peripheral devices into host computing devices is presented. A method includes, over a network interface of a host device, obtaining an indication of a peripheral device available for associating with the host device. Based on the indication, the method includes initiating instantiation of the peripheral device into a Peripheral Component Interconnect Express (PCIe) subsystem of the host device by at least emulating behavior of the peripheral device over the network interface as a PCIe peripheral device coupled locally to the host system.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 30, 2024
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Allen R. Andrews, Henry Lee Harris
  • Patent number: 11829264
    Abstract: Methods, systems, and computer-readable media (transitory or non-transitory) are described herein for automatic backup and replacement of a storage device. According to an example, a storage failure for given storage device may be predicted. A backup process of the give storage device to a remote system may be initiated based on predicting the storage failure for the given storage device. The backup process may create a one-to-one image backup or a user data backup based on a predicted amount of time until the storage failure of the given storage device. A restore process of a new storage device at the remote system may be initiated upon completion of the backup process. The restore process may depend on the backup created during the backup process and/or various types of new storage devices that are available. The new storage device may be based on the given storage device.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 28, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Maikel Maciel Ronnau, Leonardo Rodriguez Heredia
  • Patent number: 11809363
    Abstract: A method for debugging an electronic subsystem is disclosed. The method includes converting a first message in a first protocol format received at a first functional logical block of a plurality of functional logical blocks of an electronic subsystem into a second message in a second protocol format at the first functional logical block, wherein the second message includes a unique identifier (UID), and generating a first trace file corresponding to the first functional logical block, wherein the first trace file includes the UID. The method includes forwarding the second message from the first functional logical block to a second functional logical block. The method includes generating a second trace file corresponding to the second functional logical block, wherein the second trace file includes the UID, and performing an analysis on the first and the second functional logical blocks.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: November 7, 2023
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir
  • Patent number: 11805024
    Abstract: Collectors are provided to network devices of an existing computer network. A reference network type associated with the existing computer network is determined. Based at least in part on telemetry and configuration information received from the collectors and the reference network type, an intent-based network model of the existing computer network is generated. The existing computer network is validated using the generated intent-based network model.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 31, 2023
    Assignee: Apstra, Inc.
    Inventors: Raghavendra Rachamadugu, Aleksandar Luka Ratkovic
  • Patent number: 11533409
    Abstract: An example image forming apparatus includes a communication device including a physical layer protocol chip for performing communication with a network by using a connector with a light emitting element for displaying a network connection state and a physical layer protocol, a print engine to perform a print job, and a processor to, based on print data being received through the communication device, control the print engine to print the received print data, determine whether a network cable is connected to the connector based on an operation state of the light emitting element, and, based on a determination that the network cable is not connected to the connector, control the physical layer protocol chip to be in a power-saving state.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 20, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jin-Woo Lee
  • Patent number: 11461018
    Abstract: Directly writing snapshot data for a volume on a storage system to an external storage includes receiving a write of new data to a portion of the storage system, forming encapsulated data by encapsulating either the new data or data at the portion of the storage system in a format that is native to the storage system, and directly writing the encapsulated data to the external storage. The external storage may be cloud storage or may be a tape emulation unit. The data at the portion of the storage system may be encapsulated prior to writing the new data to the storage system. The new data may be encapsulated. Prior to receiving a write of the new data, a full backup may be performed from the storage system to the external storage. The encapsulated data may provide an incremental backup for the full backup.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 4, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Brett A. Quinn, Paul A. Linstead, Douglas E. LeCrone
  • Patent number: 11409608
    Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Shrikanth Ganapathy, Ross V. La Fetra, John Kalamatianos, Sudhanva Gurumurthi, Shaizeen Aga, Vilas Sridharan, Michael Ignatowski, Nuwan Jayasena
  • Patent number: 11392524
    Abstract: An interface module for coupling data buses to first signal line ports, to which signal lines of at least one first data bus are connectable, and second signal line ports, to which signal lines of at least one second data bus are connectable, has at least one connecting device for making at least one connection between one of the first signal line ports and one of the second signal line ports. In this case, the first signal line port connected to the second signal line port is alternately connectable to at least one other second signal line port and/or the second signal line port connected to the first signal line port is alternately connectable to at least one other first signal line port. A related system has at least one such interface module and at least one apparatus that has the at least one first data bus and/or at the least one second data bus.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 19, 2022
    Assignee: Harting Electric GmbH & Co. KG
    Inventors: Markus Friesen, Lutz Tröger
  • Patent number: 11386519
    Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Kun Tian, Yao Zu Dong, Zhiyuan Lv
  • Patent number: 11368829
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Young Choi, Dong Yun Kim, Ivan Galkin, Ji-Hoon Park, Jong-Jin Lee
  • Patent number: 11363437
    Abstract: A near-field communication (“NFC”) tag identifier (ID) associated with an establishment obtain by scanning an NFC tag at a location in the establishment using a wireless device of a patron is received. Login credentials associated with the patron and the wireless device are received. A location of the patron in the establishment is determined from the login credentials associated with the patron and the wireless device, and from the NFC tag ID. An available service of the establishment is communicated to the wireless device of the patron based on the login credentials associated with the patron and the wireless device, and from the NFC tag ID. The identified location is associated with exact order items so the service staff is able to keep track of an order made by the patron.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 14, 2022
    Assignees: Quickze Inc
    Inventors: Rajesh Tiwari, Archana Deshpande, Archit Peshave
  • Patent number: 11360674
    Abstract: A magazine-based data storage library in connection with a disk drive-based archive storage system is described that essentially generates parity data for tape formatted data streams (stored to tape cartridges) that do not align by way of data blocks or file marks. Data streams intended for tape storage sent to tape cartridges are also sent to a disk drive storage system via an encoder where parity of the data streams can be generated. More specifically, the encoder digitally formats tape blocks and tape marks (as well as other tape formatted structure) in a digital stream of data that can be added to other encoded digital streams of data to generate parity. To reconstruct a specific tape cartridge from a tape set, the encoded data from each of the tapes in the tape set are subtracted from the parity data and the remaining encoded data is decoded and sent to a designated tape cartridge.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 14, 2022
    Assignee: Spectra Logic Corporation
    Inventor: Joshua Daniel Carter
  • Patent number: 11327915
    Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Francois Cloute, Christophe Taba
  • Patent number: 11327725
    Abstract: Systems and methods may aggregate and organize implicit and explicit initialization, reset, and termination operations defined throughout the hierarchy of an executable. The systems and methods may analyze the model and identify implicit and explicit initialization, reset, and termination operations defined at various hierarchical levels. The systems and methods may aggregate the implicit and explicit initialization, reset, and termination operations into an initialize callable unit, a reset callable unit, and a termination callable unit. The systems and methods may apply optimizations to the callable units, and resolve conflicts. The systems and methods may define a single entry point for each of the initialize, reset, and termination callable units.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 10, 2022
    Assignee: The MathWorks, Inc.
    Inventors: Peter S. Szpak, Biao Yu, Alongkrit Chutinan
  • Patent number: 11314543
    Abstract: An improved architecture is provided which enables significant convergence of the components of a system to implement virtualization. The infrastructure is VM-aware, and permits scaled out converged storage provisioning to allow storage on a per-VM basis, while identifying I/O coming from each VM. The current approach can scale out from a few nodes to a large number of nodes. In addition, the inventive approach has ground-up integration with all types of storage, including solid-state drives. The architecture of the invention provides high availability against any type of failure, including disk or node failures. In addition, the invention provides high performance by making I/O access local, leveraging solid-state drives and employing a series of patent-pending performance optimizations.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 26, 2022
    Assignee: Nutanix, Inc.
    Inventors: Mohit Aron, Dheeraj Pandey, Ajeet Singh, Rishi Bhardwaj, Brent Chun
  • Patent number: 11294878
    Abstract: A data structure that includes border data structures that appear at the respective interfaces between each of at least some of the segments in the data structure. The border does not conform to a data format for any of the elemental data types of the elemental data items represented within the data structure, and does not represent a size of any of the neighboring segments. Second, the data structure also includes an index. When writing the data structure, the writer tracks the position of each of the regions. When all segments and regions have been written, the writer can then write an index that represents the position of each region. The reader can then use that index to quickly read from only those regions of interest, and quickly skip over regions not of interest.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: April 5, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Scott M. Louvau, Michael C. Fanning
  • Patent number: 11263032
    Abstract: The disclosed computer-implemented method for emulating local storage may include (i) exposing a cloud storage as a local block storage device by providing a translation service that translates commands formatted according to an operating system compatibility standard protocol into commands formatted according to a cloud storage application programming interface protocol, the cloud storage dividing a cloud storage volume into multiple objects, (ii) receiving a command that is formatted according to the operating system compatibility standard protocol and that specifies a length and offset of the cloud storage volume, (iii) translating the command into a translated command formatted according to the cloud storage application programming interface protocol, and (iv) returning a result of executing the translated command. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 1, 2022
    Assignee: Veritas Technologies LLC
    Inventors: Nalini Kumari Nallamalli, Utkarsh Naiknaware, Raosaheb Jadhav, Kushal Kumaran, Anindya Banerjee
  • Patent number: 11221767
    Abstract: The disclosure provides an approach for testing if a cache line of a cache has been flushed to non-volatile memory (NVM). The approach generally includes reading, by a central processing unit (CPU), data from the NVM. The approach further includes storing, by the CPU, a copy of the data in the cache as a cache line. The approach further includes modifying, by the CPU, at least a portion of the copy of the data in the cache. The approach further includes requesting, by the CPU, the cache line be flushed to the NVM. The approach further includes performing, by the CPU, one or more instructions in parallel to the cache line being flushed to the NVM. The approach further includes requesting, by the CPU, a state of the cache line and determining if the cache line has been persisted in the NVM based on the state of the cache line.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 11, 2022
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Aasheesh Kolli
  • Patent number: 11209991
    Abstract: Disk based emulation of tape libraries is provided with features that allow easier management and administration of a backup system and also allow increased flexibility to both archive data on tape at a remote location and also have fast restore access to archived data files. Features include automatic emulation of physical libraries, and the retention and write protection of virtual tapes that correspond to exported physical tapes.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 28, 2021
    Assignee: Overland Storage, Inc.
    Inventors: Victoria Gonzalez, Sergio Encarnacao
  • Patent number: 11175840
    Abstract: An apparatus in one embodiment comprises a host device comprising a processor coupled to memory. The host device is configured to communicate over a network with at least one storage system. The host device is further configured to generate a user space block device and to generate a kernel space block device corresponding to the user space block device. The host device is further configured to receive an input-output operation at the kernel space block device from an application executing on the host device and to transfer the input-output operation from the kernel space block device to the corresponding user space block device. The host device is further configured to submit the input-output operation to the at least one storage system based at least in part on the user space block device.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Md Haris Iqbal, Kundan Kumar
  • Patent number: 11175984
    Abstract: This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error (EC) information, which is linearly combined with similar information from other drives to create “superparity.” If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are use, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 16, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Robert Lercari, Craig Robertson, Mike Jadon
  • Patent number: 11157625
    Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 26, 2021
    Assignee: Dell Products, L.P.
    Inventor: Craig Lawrence Chaiken
  • Patent number: 11113091
    Abstract: An apparatus, method and computer program are described, the apparatus comprising processing circuitry configured to execute software, and an interface configured to receive, from the processing circuitry, a configuration request from first software requesting configuration of a virtualised device. In response to the configuration request, the interface is configured to forward a mediated request to the processing circuitry, and the mediated request comprises a request that second software having a higher privilege level than the first software determines a response to the configuration request received from the first software.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 7, 2021
    Assignee: Arm Limited
    Inventors: Alexandre Romana, Mario Torrecillas Rodriguez, Eric Biscondi
  • Patent number: 11095709
    Abstract: A hybrid cloud computing system having a private data center and a public cloud computing system is discussed. The private data center is managed by a first organization. The public cloud computing system is managed by a second organization, and the first organization is a tenant in the public cloud computing system. The hybrid cloud computing system is configured to generate a mapping that contextualizes virtual objects migrated between the private data center and the public cloud computing system based on the objects' location. Such a mapping is maintained to expose the true hybridity of the hybrid cloud rather than present two distinct views of a private data center (or private cloud) and a public cloud.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 17, 2021
    Assignee: VMware, Inc.
    Inventors: Sachin Thakkar, Debashis Basak, Serge Maskalik, Mark Bryan Whipple, Aarti Kumar Gupta
  • Patent number: 11029867
    Abstract: A memory system may include: a nonvolatile memory device including a plurality of memory blocks; and a controller for reading data stored in a physical address in response to a read command from a host, the read command including a first logical address, a first physical address corresponding to the first logical address, and a first read count associated with the first physical address, the controller may read first data from a first block corresponding to the first physical address and sends a response to the read command to the host, the response including the first data and updated information relating to the first read count.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Hwan Lee
  • Patent number: 11029934
    Abstract: A method includes analyzing operational code to determine identifiers used within the operational code. The method further includes grouping like identifiers based a relational aspect of the identifiers. The method further includes, for one or more identifier groups, determining potential feature(s) of the identifier group(s). The method further includes testing the potential feature(s) based on a corresponding feature test suite to produce feedback regarding meaningfulness of the potential feature(s). The method further comprises, when the meaningfulness is above a threshold, adding the potential feature(s) to a feature set. The method further includes, when the meaningfulness is at or below the threshold, adjusting analysis parameter(s), grouping parameter(s), feature parameter(s), and/or testing parameter(s).
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 8, 2021
    Assignee: UniqueSoft, LLC
    Inventor: Thomas J. Weigert
  • Patent number: 10996975
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
  • Patent number: 10996967
    Abstract: First and second virtual storage controllers represent first and second physical storage controllers that provide access to different physical storage devices that back first and second virtual disks. One or more computing nodes host a virtual storage array that includes paired virtual storage directors. Each virtual storage director has access to both the first and second virtual storage controllers. Thus, the virtual disks may be presented to the storage directors as dual-ported disks even if the physical storage devices are single-ported. The virtual storage directors and virtual storage controllers may each be hosted by a separate virtual machine or instantiated in a separate container.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 4, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jonathan Krasner, Chakib Ouarraoui, Steven McClure
  • Patent number: 10992543
    Abstract: Collectors are provided to network devices of an existing computer network. A reference network type associated with the existing computer network is determined. Based at least in part on telemetry and configuration information received from the collectors and the reference network type, an intent-based network model of the existing computer network is generated. The existing computer network is validated using the generated intent-based network model.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 27, 2021
    Assignee: Apstra, Inc.
    Inventors: Raghavendra Rachamadugu, Aleksandar Luka Ratkovic
  • Patent number: 10972540
    Abstract: Provided are a method, system and program for requesting storage performance models for a configuration pattern of storage resources to deploy at a client computing environment. A determination is made of a new configuration pattern of storage resources to deploy. A request is sent to a service provider with information on the new configuration pattern. A result set is received from the service provider having at least one provided configuration pattern having a degree of similarity to the new configuration pattern and a storage performance model for each of the provided configuration patterns. Each of the storage performance models indicate workload and performance characteristics for one of the provided configuration patterns. One of the provided configuration patterns is selected from the result set and the storage performance model for the selected configuration pattern is used to model performance at the client.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rakesh Jain, Ramani R. Routray, Sumant Padbidri, Yang Song
  • Patent number: 10949134
    Abstract: A first screen associated with printer queues is displayed in response to a user operation, and an output process of a document is executed using a printer queue selected on the first screen by a user operation.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 16, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Daisuke Yamazaki
  • Patent number: 10853280
    Abstract: A storage system includes a storage engine having a first compute node, a second compute node, a first fabric adapter, and a second fabric adapter, the first compute node having a first memory and the second compute node having a second memory. The first compute node is connected to both the first and second fabric adapters, and the second compute node is connected to both the second and first fabric adapters. Both fabric adapters are configured to perform atomic operations on a memory of its respective compute node, and each fabric adapter contains a multi-initiating module configured to enable both the first compute node and the second compute node to initiate memory access operations on its respective memory.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: James Guyer, Jason Duquette, Alesia Tringale, Julie Zhivich
  • Patent number: 10831489
    Abstract: Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak K. Singh
  • Patent number: 10817204
    Abstract: Facilitating migration of versioned data in a reverse chronological order is provided herein. A system can comprise a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can comprise initiating a migration of information from a source storage device to a target storage device. The information can comprise a current object version of data and previous object versions of the data. The current object version of data can comprise portions of the previous object versions of the data. The operations can also comprise facilitating a first migration of the current object version prior to the migration of the previous object versions. Further, the operations can comprise facilitating a second migration of the previous object versions in a reverse migration order.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: October 27, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Mikhail Borisov
  • Patent number: 10789001
    Abstract: Methods, systems, and apparatus, including a managed device comprising memory storage, one or more control registers, and circuitry to perform operations of receiving, from a control system, one or more posted write operations directed to the one or more control registers; based on the one or more posted write operations, storing in the one or more control registers, data specifying at least a system address of a memory of the control system, where the system address corresponds to a starting address of a predetermined section of the memory; and transferring managed device data from the memory storage to the predetermined section of the memory of the control system by issuing, to the control system and based on the system address of the memory, one or more posted write operations to write the managed device data to the predetermined section of the memory.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 29, 2020
    Assignee: Innovium, Inc.
    Inventors: Mani Kumaran, Mohammad Kamel Issa, Gururaj Ananthateerta
  • Patent number: 10754648
    Abstract: A microprocessor having the capability of executing a micro-instruction for series calculation is provided. The microprocessor includes an instruction decoder and an execution circuit for series calculation. The micro-instruction whose source operands correspond to an undetermined number x and a plurality of coefficients a0 to an (for x0 to xn) is decoded by the instruction decoder. Based on x and a0 to an, the execution circuit for series calculation includes at least one multiplier for calculating exponentiation values of x (e.g. xp), and includes at least one MAU (multiply-and-accumulate unit) for combining x, the exponentiation values of x, and the coefficients a0 to an for the series calculation.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: August 25, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Weilin Wang, Jiin Lai
  • Patent number: 10719273
    Abstract: SCSI commands that are not supported by a client terminal can be enabled. In scenarios where the client terminal's operating system may not support the same SCSI commands as the server's operating system, a redirected mass storage device that does support the same SCSI commands as the server's operating system can still be initialized on the server as supporting these SCSI commands. Then, to allow the SCSI commands that are not supported by the client terminal's operating system to be provided to the mass storage device, a client-side proxy can employ a SCSI Pass Through Interface to send the unsupported commands rather than providing them to the client-side disk driver. The proxy may still provide supported SCSI commands to the client-side disk driver for typical handling.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 21, 2020
    Assignee: Wyse Technology L.L.C.
    Inventor: Gokul Thiruchengode Vajravel
  • Patent number: 10691249
    Abstract: An electronic device, an electronic system, or a method may be used for testing an electronic device. The electronic device may include a virtual touch circuit. The virtual touch circuit may be configured to transmit testing data. The testing data may represent sensory input data. The electronic device may include a touch host controller. The touch host controller may be configured to process sensory data inputs. The sensory data inputs may include the testing data. The electronic device may include a validation circuit. The validation circuit may be configured to evaluate performance of the touch host controller. The validation circuit may evaluate the performance of the touch host controller by using the testing data that was processed by the touch host controller. The touch host controller, the virtual touch circuit, and the validation circuit may be included in a single die.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventor: Lakshminarayana Pappu
  • Patent number: 10694023
    Abstract: A testing method for testing mobile communication devices comprises transmitting, by a testing front end module, a testing profile associated with a Universal Integrated Circuit Card, UICC, to a mobile communication device, activating the testing profile on the mobile communication device, setting, by a testing controller, the configuration of the mobile communication device to a testing mode according to the information of the activated testing profile of the UICC, and performing operational tests on the mobile communication device using a testing front end module of a testing system while the configuration of the mobile communication device is set to the testing mode.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: June 23, 2020
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Uwe Baeder, Holger Jauch
  • Patent number: 10666507
    Abstract: Various technologies described herein pertain to controlling reconfiguration of a dependency graph for coordinating reconfiguration of a computing device. An operation can be performed at the computing device to detect whether an error exists in the dependency graph for a desired configuration state. The dependency graph for the desired configuration state specifies interdependencies between configurations of a set of features. An error can be detected to exist in the dependency graph when the desired configuration state differs from an actual configuration state of the computing device that results from use of the dependency graph to coordinate configuring the set of features. Feedback concerning success or failure of the dependency graph on the computing device can be sent from the computing device to a configuration source. The dependency graph can be modified (by the computing device and/or the configuration source) based on whether an error is detected in the dependency graph.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shayak Lahiri, Sean Anderson Bowles, Peter J. Kaufman
  • Patent number: 10642827
    Abstract: Functionality is described herein for presenting representations of the z most recently presented items. The functionality also presents indicators which convey the presentation modes that were last used to present the z items. When the user selects one of the z items, the functionality presents it, as a default, using the last-used presentation mode, as conveyed by the indicator associated with this item. In one particular case, the last-used presentation mode corresponds to a full mode or a snap mode.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 5, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John E. Churchill, Joseph Wheeler, Jérôme Jean-Louis Vasseur, Thomas R. Fuller, Jason D. Giles
  • Patent number: 10638601
    Abstract: Systems and methods for routing of conductive traces in a printed circuit board are described. In one embodiment, the method may include routing a first trace in a first layer of a printed circuit board of a solid state drive, routing a second trace in a second layer of the printed circuit board, and routing the first trace and the second trace between a serializer/deserializer (SerDes) of a first controller of the solid state drive and a SerDes of a second controller of the solid state driver. In some cases, the first trace and the second trace may be configured to transmit differential signals to communicate data between the first controller and the second controller. In some embodiments, the second layer may be adjacent to the first layer.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 28, 2020
    Assignee: Seagate Technology LLC
    Inventors: Vinod Arjun Huddar, Abhishek Laguvaram
  • Patent number: 10623701
    Abstract: Disclosed is a system that includes a computing device, a presentation system, and a hardware module disposed between the computing device and the presentation system. The hardware module and the computing device each may be configured to exchange a signal that includes media data and emulated input/output (“I/O”) data, audio/visual data (“A/V”); the hardware module may also be configured to supply power to the computing device. The signal and the supplied power may be communicated between the hardware module and the computing device over a single cable.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Facebook, Inc.
    Inventors: Peter John Richard Gilbert Bracewell, Howard William Winter, Oliver Pell
  • Patent number: 10621354
    Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 14, 2020
    Assignee: Dell Products, L.P.
    Inventor: Craig Lawrence Chaiken
  • Patent number: 10579292
    Abstract: New, more efficient and robust data storage devices and techniques are provided. In some aspects of the invention, a new form of data storage device is provided, incorporating storage units with simple writeable domains, and a readable conditioning structure positioned around the units. The readable structure elaborates the simpler data written in the domains to generate more complex and complete data sets. In some embodiments, the physical arrangement, or other attributes, of structural storage device elements may serve as the patterned reference device for data enhancement and supplementation.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 3, 2020
    Inventor: Christopher V. Beckman
  • Patent number: 10572369
    Abstract: A method for monitoring errors when testing a control program of a control device in a simulation environment, the control program being executed by an emulator on a computer, the emulator assigning an extended range of items to program variables of the control program, a variable value allocated to a program variable being stored in the extended range of items, the emulator marking program variables as erroneous or non-erroneous, the marking being carried out on the basis of an assignment of non-erroneous program variables to a first category and of erroneous program variables to a second category, or the marking being carried out on the basis of an error field stored in the extended range of items, a validity value being allocated to the error field of a non-erroneous program variable and an error value being allocated to the error field, of an erroneous program variable.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 25, 2020
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventor: Thorsten Hufnagel
  • Patent number: 10565068
    Abstract: A backup copy of a production device is used to quantify suitability of host application data for placement on individual managed drives and virtualized managed drives based on storage capabilities associated with those drives. A data analysis program on a data backup storage array may generate block backup statistics to indicate that a production device or certain chunks, blocks or volumes of host application data are highly compressible or reducible via deduplication. The block backup statistics are sent from the data backup storage array to the primary storage array. The primary storage array uses the block backup statistics to select a particular storage resource with suitable storage capabilities for the data. Highly compressible data may be stored on a storage virtualization storage array with data compression capability, and data that is neither highly compressible nor reducible with deduplication may be stored on local resources.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Arieh Don, Gabriel Benhanokh, Ian Wigmore, Stephen Smaldone
  • Patent number: 10545854
    Abstract: The present disclosure is related in general to software testing and a method and a system for automatically identifying violation in the test cases. A test case validation system categorizes the test cases into event-based test cases and binary test cases. Further, a Part-Of-Speech (POS) pattern is detected in the one or more test cases based on POS tags assigned to each of the tokens in test cases. Thereafter, comparison of the detected POS pattern and the one or more tokens with predefined POS patterns and predefined tokens identifies violations in the one or more test cases if any, using pattern matching and Natural Language Processing (NLP). The predefined POS patterns and tokens used for comparison are filtered based on category of the test case thus accelerating the process of the violation identification. The test case validation system is capable of accurately identifying more than one type of violations simultaneously.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 28, 2020
    Assignee: Wipro Limited
    Inventors: Aman Chandra, Varun Anant