Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

Abstract: A data processing apparatus includes a master device configured to transmit commands for destinations, a slave device including a plurality of command processing regions respectively corresponding to the destinations, and a controller configured to relay communication between the master device and the slave device. The controller assigns time stamp value to the commands as an initial value when the commands was received by the controller and increment the time stamp value every command arbitration cycle, selects a command having a largest time stamp value among the commands in a tournament manner by comparing commands having different destinations every command arbitration cycle, stores a command selection history of each comparison of commands, selects the command based on a command selection history corresponding to the compared commands when respective time stamp values of the compared commands are the same or substantially the same as each other.

Abstract: A communication architecture, for exchanging data between processing units that are intended to operate in parallel comprises a communication system comprising a set of interfaces each intended to be linked to a processing unit, a set of sequencers that are able to define, for each processing unit, time intervals of access to a shared memory accessible by the processing units for writing and reading data, for the sequential arbitration of accesses to said memory, and a set of address managers able to allocate each processing unit ports for access to the shared memory.

Abstract: The in-vehicle network includes a plurality of slave devices and a master device that communicates with the plurality of slave devices. The plurality of slave devices generates slave unique information as random information upon setting ID, and transmits the generated slave unique information. When all the slave unique information received from the plurality of slave devices are different from each other, the master device sets the ID based on each slave unique information. When the slave unique information received from the plurality of slave devices matches, the master device transmits a regeneration command to regenerate the slave unique information. Upon receiving the regeneration command, the slave device regenerates the slave unique information.

Abstract: Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: assigning resources of a K-tier resource pool to a certain job residing in a job queue, wherein the certain job residing in the job queue features job coupling characterized by an independent job and a dependent job which for completion depends on an output of the independent job, wherein the K-tier resource pool includes at least one foreground virtual machine (VM) having a first central processing unit (CPU) priority and at least one background virtual machine (VM) having a second CPU priority, wherein the first CPU priority is higher than the second CPU priority, wherein the assigning resources of the K-tier resource pool to the certain job includes assigning one or more foreground VM to the independent job and assigning one or more background VM to the dependent job.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: A data processing device includes a first sub-arbiter configured to arbitrate an access by first and second masters that access data stored in a memory; a second sub-arbiter configured to arbitrate an access to the memory by a plurality of masters other than the first and the second masters; a main arbiter configured to prioritize the access to the memory by the first sub-arbiter over the access to the memory by the second sub-arbiter; and a limiting unit configured to limit an amount of the access to the memory by the second master within a preset range.

Abstract: An organization categorization system and method is disclosed. The organization categorization system and method relies on server data to discover which business organizations are consuming the finite resources of the server and in what proportions. Organizations are categorized according to their consumption of resources. The categorization system and method further ascribes a relative business value to each organization to facilitate the allocation of resources among the various organizations in a business. In an example embodiment, users of the server resources use the SAS programming language and the server resources execute SAS applications that support the SAS programming language. The organization categorization system and method connects an executed computer program to a business-defined classification of applicability to purpose.

Abstract: A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

Abstract: In one example in accordance with aspects of the present disclosure, an expander is provided. The expander comprises a workload scheduling module to cause the expander to enter a first mode of operation where the expander processes interrupts, and further to enter a second mode of operation where the expander processes interrupts for up to a predetermined time period before responding to at least one of Serial Management Protocol (SMP) commands and Serial SCSI Protocol (SSP) commands with a retry message.

Abstract: A control and communication system including a number of automation units which are adapted to process signals in function plans within the automation unit and which are connected in the same level to a common communication bus for providing a peer-to-peer communication between the automation units, further includes an engineering unit being connected to the communication bus and being adapted to provide functions allowing at least one automation unit to exchange signals to a function plan which is attributed to another automation unit.

Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.

Abstract: A system including a first communication module to transmit or receive data via an antenna in accordance with a first communication standard; a second communication module to transmit or receive data via the antenna in accordance with a second communication standard; and an arbitration module. The arbitration module outputs a first mutual grant where both the first communication module and the second communication module are able to simultaneously transmit data via the antenna; a second mutual grant where both the first communication module and the second communication module are able to simultaneously receive data via the antenna; a third mutual grant where the first communication module and the second communication module are able to simultaneously transmit and receive data, respectively, via the antenna; and a fourth mutual grant where the first communication module and the second communication module are able to simultaneously receive and transmit data, respectively, via the antenna.

Abstract: An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.

Abstract: An apparatus including a first register, a second register, and a control logic. The first register may be configured to store requests from a plurality of clients for a current cycle. The second register may be configured to store an indicator value indicating which of the plurality of clients received a grant in a previous cycle. The control logic may be configured to determine which of the plurality of clients having a request in the current cycle receives a grant based upon (i) a pointer value and (ii) the indicator value.

Abstract: An integrated circuit device (100) comprising a first plurality of components (102-112), a second plurality of buses (114-124, 140, 142) for transmitting transaction requests from said components (102-112) to a resource (138) shared by said components (102-112) and a third plurality of arbiters (132-136) arranged in at least two levels of arbitration. Each transaction request has attached priority value that is used by the arbiters to determine which of the components should be granted access to the resource (138).

Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: A storage system may include a set of storage devices; a controller; and a management device. The controller may arbitrate among operations for execution by the set of storage devices, where the operations are received from users that are associated with priority levels. The controller may maintain queues, corresponding to the users, to queue operations from the users. The controller may additionally include a scoring component and a scheduler. The scoring component may maintain a score for each queue. The scheduler may choose, from the queues and based on the score of each queue, one of the operations to service. The management device may receive usage updates, from the controller, reflecting usage of the set of storage devices; calculate a maximum allowed usage levels, based on the received usage updates, for each user; and transmit the calculated maximum usage levels to the controller.

Abstract: Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.

Abstract: Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plural functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.

Abstract: Techniques for ensuring deterministic thread context switching in a virtual machine application program include, in one embodiment, providing a single application-level mutex that threads of the executing application program are forced to acquire to execute application code of the virtual machine application program. During a first recorded execution of the virtual machine application program, a record is created and stored in a computer that indicates the order in which threads acquire the application-level mutex.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: Hardware resources sharing for a computer system running software tasks. A controller stores records including a mutex ID tag and a waiter flag in a cache. Lock and unlock registers are readable by the controller and loadable by the tasks with a mutex ID specifying a hardware resource. The controller monitors whether the lock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it sets the record's waiter flag. If not, it adds a record having a tag corresponding with the mutex ID. The controller also monitors whether the unlock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it determines whether that record's waiter flag is set and, if so, it clears that record from the cache.

Abstract: A communication system is provided, including a first master device to operate as a master of a communication according to a first protocol, a second master device to operate as a master of a communication according to a second protocol, a common slave device to operate as a slave of the communication according to the first protocol and the second protocol with respect to the first master device and the second master device, and a switch to control a connection between the common slave device and the first master device and between the common slave device and the second master device for a communication between the common slave device and one of the first master device to and the second master device. Thus, embodiments of the present invention provide a communication system that minimizes cost increases and improves communication speed in a system in which a plurality of master devices communicate with a slave device performing the same function as the master devices.

Abstract: An on-chip Radio Frequency (RF) Interconnect (RF-I) for communication between internal circuit nodes of an integrated circuit is provided. In one embodiment, an integrated circuit is provided that includes an on-chip transmission line, a first circuit node associated with an RF transmitter connected to the transmission line, and a second circuit node associated with an RF receiver connected to the transmission line. In order to transmit data from the first circuit node to the second circuit node, the RF transmitter associated with the first circuit node modulates the data onto an RF carrier frequency to provide a modulated RF signal and transmits the modulated RF signal over the transmission line. The RF receiver associated with the second circuit node receives the modulated RF signal from the transmission line and demodulates the modulated RF signal to recover the data for the second circuit node.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.

Abstract: A wireless network device including an antenna, a first communication module, and a second communication module. The first communication module is configured to transmit or receive packets of data in accordance with a first communication standard, and the second communication module is configured to transmit or receive packets of data in accordance with a second communication standard. The wireless network device further includes an arbitration module configured to grant access of each of the first communication module and the second communication module to the antenna so that the first communication module and the second communication module can respectively transmit or receive data packets in accordance with the first communication protocol and the second communication protocol.

Abstract: Methods, apparatus, and computer-readable media for management and arbitration of dedicated mobile communication resources for mobile applications are provided. Mobile applications can be given a priority level that establishes an importance with respect to one or more other mobile applications and at least one mobile resource. If competing applications attempt to access the mobile resource concurrently, access can be provided to an application having higher priority level. Furthermore, control of a resource can be taken away from an application having lower priority in order to affect control of such resource for a higher priority application. In one aspect, a privilege code of an application can be verified prior to establishing control of the resource for the application, to mitigate a likelihood of inappropriate transfer of resources.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).

Abstract: A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: A deadlock prevention mode indicator is provided, wherein the deadlock prevention mode indicator is a lock that can be held in a shared mode or in an exclusive mode by one or more of a plurality of threads, and wherein the plurality of threads can cause deadlocks while acquiring a plurality of data locks. An execution of the plurality of threads is serialized by allowing a data lock to be acquired by a thread in response to the thread holding the deadlock prevention mode indicator, wherein serializing the plurality of threads avoids any deadlock from occurring.

Abstract: A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.

Abstract: A method and an apparatus ensuring protection of digital data are provided. In addition to re-encrypting the data using an unchangeable key, the data is double re-encrypted using a changeable key. The changeable key is used first and the unchangeable key is then used, or in another case, the unchangeable key is used first, and the changeable key is then used. In the aspect of embodiments, there is a case adopting a software, a case adopting a hardware, or a case adopting the software and the hardware in combination. The hardware using the unchangeable key developed for digital video is available. In adopting the software, encryption/decryption is performed in a region below the kernel which cannot be handled by the user to ensure the security for the program and for the key used. More concretely, encryption/decryption is performed with RTOS using a HAL and a device driver, i.e., a filter driver, a disk driver and a network driver, in an I/O manager.

Abstract: Various embodiments provide methods and systems operable to receive a work queue pair from one of a plurality of host nodes, to scan the work queue pair for known data formats corresponding to one of a plurality of transport protocols, to optionally convert the work queue pair to produce a standard work queue pair data format, to add the work queue pair to a scheduler queue for a virtual host channel adapter (HCA) scheduler, and to update a context associated with the work queue pair.

Abstract: An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator is defined to consider a different portion of the multiple requestors when selecting a requestor to be serviced by the master to which the arbitrator is assigned. Each arbitrator is further defined to select a requestor from the different portion of the multiple requestors, such that selection of a particular requestor is not duplicated among the plurality of arbitrators. Additionally, requestor selection by each of the plurality of arbitrators is performed in a same clock cycle.

Abstract: A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined to select a different one of the multiple requestors to be serviced by the master to which the arbitrator is assigned. Also, the plurality of arbitrators is defined to make their requestor selections in the same clock cycle. Additionally, the plurality of arbitrators is defined to make their requestor selections such that selection of a particular requestor is not duplicated among the plurality of arbitrators.

Abstract: A wireless network device includes a first communication module to communicate with at least one of first devices and a second communication module to communicate with at least one of second devices. An arbitration module receives a request for communication from the first communication module, detects when the second communication module is communicating in a locked mode, and denies request for communication from the first communication module when the second communication module is communicating in the locked mode. Transmission or reception of a packet in the locked mode is not interrupted to avoid loss of the packet. The arbitration module grants the request for communication from the first communication module when the second communication module is communicating in the locked mode and when granting the request for communication from the first communication module does not require stopping the second communication module from communicating in the locked mode.

Abstract: Aspects of the subject matter described herein relate to detecting the ready state of a user interface element. In aspects, a synchronization object is created to indicate when a user interface element is ready. Data is then loaded into the user interface element. After the data is loaded, an indication is made via the synchronization object that the user interface element is ready. After this occurs, a thread waiting on the synchronization object may interact with the user interface element with confidence that the user interface element is ready.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.