Shared Memory Area Patents (Class 711/147)
  • Patent number: 11940994
    Abstract: Techniques are disclosed that relate to manipulating a chain of database objects without locking the chain. A computer system may maintain a chain that orders a set of database objects stored in a cache of the computer system. The computer system may receive a set of requests to perform database transactions. Based on those received set of requests, the computer system may determine to perform a plurality of chain operations that involve modifying the chain. The computer system may perform two or more of the plurality of chain operations at least partially in parallel using a set of atomic operations without acquiring a lock on the chain.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Salesforce, Inc.
    Inventors: Rui Zhang, Prateek Swamy, Yi Xia, Punit B. Shah, Rama K. Korlapati
  • Patent number: 11934827
    Abstract: An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 19, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sooraj Puthoor, Muhammad Amber Hassaan, Ashwin Aji, Michael L. Chu, Nuwan Jayasena
  • Patent number: 11921635
    Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventor: Altug Koker
  • Patent number: 11914544
    Abstract: According to one embodiment, a memory system includes a board, a memory controller, and a semiconductor memory. When a signal input to a third port or a command received from an outside of the memory system satisfies a first condition, the memory controller is configured to use a first port as a first signal port and to use a second port as a second signal port. When the signal input to the third port or the command received from the outside of the memory system satisfies a second condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Nana Kawamoto, Naoki Kimura
  • Patent number: 11914546
    Abstract: An information handling system includes a memory and a baseboard management controller. The memory stores one or more device update packages, and each of the first device update packages includes an inter-integrated circuit payload. The baseboard management controller receives a first device update package, and stores the first device update package in the memory. In response to the first device update package being stored in the memory, the baseboard management controller launches a handler. The baseboard management controller retrieves a bus number and an address for a target device identified in the first device update package. The baseboard management controller parses data in a body of the inter-integrated circuit payload of the first device update package, and executes inter-integrated circuit commands in the body to provide a firmware image update to the target device.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: February 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Yogesh P. Kulkarni, Chandrasekhar Mugunda, Rui An, Akshata Sheshagiri Naik
  • Patent number: 11907577
    Abstract: A plurality of commands is received from at least one application. A command of the plurality of commands is to be performed by a Data Storage Device (DSD) after one or more conditions have been satisfied by the DSD. The plurality of commands is enqueued and the command is enqueued with the one or more conditions for performing the command. It is determined whether the one or more conditions have been satisfied by the DSD, and in response to determining that the one or more conditions have been satisfied by the DSD, the command is sent to the DSD for performance of the command.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Spector, Doron Ganon, Eran Arad
  • Patent number: 11907101
    Abstract: Disclosed herein are systems and methods for selective patching processes. In one exemplary aspect, the method includes: identifying, via a user space patching service, a patch that modifies at least one function included in a process, wherein the process is executed on a computing device; generating a list of target pages in virtual memory of the computing device, wherein the list of target pages includes code associated with the at least one function; marking the target pages as non-executable based on file identification; intercepting, using an amended page-fault event handler, an attempt to execute the code associated with the at least one function by the process; and applying the patch to modify the at least one function.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 20, 2024
    Assignee: Cloud Linux Software, Inc.
    Inventors: Igor Seletskiy, Pavel Boldin
  • Patent number: 11907176
    Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: receiving a request for a lock on a page from a virtual database amongst two or more virtual databases, the virtual database including a number of containers respectively corresponding to the same number of database components of the virtual database. A copy of the page is refreshed with a latest copy of the page in an overall cache prior to granting the lock based on ascertaining that the page is not locked by any other virtual database. The virtual database is granted with the lock and have an exclusive access to the page.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Xin Peng Liu, ShengYan Sun, Shuo Li, Xiaobo Wang
  • Patent number: 11899933
    Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: February 13, 2024
    Inventors: Sompong Paul Olarig, Son T. Pham
  • Patent number: 11886987
    Abstract: A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual networks among the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first partial selection of weights within the neural network is mapped into the equivalent conductances of the networks in the columns to enable the computation of multiply-and-accumulate operations by mixed-signal computation. The logic updates the mappings to select a second partial selection of weights to compute additional multiply-and-accumulate operations and repeats the mapping and computation operations until all computations for the neural network are completed.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: January 30, 2024
    Assignee: Arm Limited
    Inventors: Shidhartha Das, Matthew Mattina, Glen Arnold Rosendale, Fernando Garcia Redondo
  • Patent number: 11861168
    Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 2, 2024
    Inventors: Sompong Paul Olarig, Son T. Pham
  • Patent number: 11853209
    Abstract: Shared memory workloads using existing network fabrics, including: presenting, by a Memory Mapped Input/Output (MMIO) translator, memory of the MMIO translator as a portion of a memory space of a host; receiving, by the MMIO translator, a first interrupt from an input/output (I/O) adapter; and storing, by the MMIO translator, without sending the first interrupt to an operating system, data associated with the first interrupt from the I/O adapter into the memory of the MMIO translator.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 26, 2023
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Connor B. Reed, Jeffrey R. Hamilton, Clifton E. Kerr
  • Patent number: 11790981
    Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
  • Patent number: 11775437
    Abstract: A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: October 3, 2023
    Assignee: Rebellions Inc.
    Inventors: Jinseok Kim, Jinwook Oh, Donghan Kim
  • Patent number: 11762773
    Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 19, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
  • Patent number: 11755465
    Abstract: In a method for superposition of multiple commands, one or more memory pages is received. The one or more memory pages include information corresponding to one or more code lines and one or more data lines. The one or more code lines correspond to a first set of layers in a memory layer and are configured to execute one or more functions. The one or more data lines correspond to a second set of layers in the memory layer and are configured to store one or more sets of data. Each of the one or more code lines from the one or more memory pages is executed to perform one or more corresponding functions, based on the one or more data lines from the one or more memory pages. A result of each of the one or more functions is stored within the one or more data lines.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 12, 2023
    Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co., Ltd.
    Inventors: Viacheslav Dubeyko, Jian Wang
  • Patent number: 11749339
    Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
  • Patent number: 11734418
    Abstract: In accordance with some embodiments, a method and system for establishing the trustworthiness of software and running systems by analyzing software and its provenance using automated means. In some embodiments, a risk score is produced. In some embodiments, software is analyzed for insecure behavior or structure. In some embodiments, parts of the software are hardened by producing possibly multiple different versions of the software with different hardening techniques applied, and a choice can be made based on user or environmental needs. In some embodiments, the software is verified and constraints are enforced on the endpoint using techniques such as verification injection and secure enclaves. In some embodiments, endpoint injection is managed through container orchestration.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: August 22, 2023
    Inventor: Joseph Alan Epstein
  • Patent number: 11727124
    Abstract: A method executing an instruction (300) to execute a query (q) for a data block (102) and determining whether the data block is stored in a block stash (370). When the data block is stored in the block stash during a download phase, the method includes removing the data block from the block stash, sending a fake query (304) to a distributed system (140) to retrieve a random data block stored in memory (114) of a distributed system (140), and discarding the random data block. When a current version of the data block is stored in the block stash during an overwrite phase, the method includes sending a fake query to the distributed system to retrieve another random data block stored in the memory of the distributed system, decrypting and re-encrypting the random data block with fresh randomness, and re-uploading the re-encrypted random data block onto the distributed system.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 15, 2023
    Assignee: Google LLC
    Inventors: Kevin Yeo, Sarvar Patel, Giuseppe Persiano
  • Patent number: 11720447
    Abstract: Techniques for achieving application high availability via application-transparent battery-backed replication of persistent data are provided. In one set of embodiments, a computer system can detect a failure that causes an application of the computer system to stop running. In response to detecting the failure, the computer system can copy persistent data written by the application and maintained locally at the computer system to one or more remote destinations, where the copying is performed in a manner that is transparent to the application and while the computer system runs on battery power. The application can then be restarted on another computer system using the copied data.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: August 8, 2023
    Assignee: VMware, Inc.
    Inventors: Pratap Subrahmanyam, Rajesh Venkatasubramanian, Kiran Tati, Qasim Ali, Marcos Aguilera, Irina Calciu, Venkata Subhash Reddy Peddamallu, Xavier Deguillard, Yi Yao
  • Patent number: 11722428
    Abstract: The reception module includes a reception buffer that is shared by the first and second transmission modules to store the packet. The first transmission module is configured to: transmit, to the second transmission module, a lending request of the reception buffer allocated to the second transmission module, based on a use amount of the reception buffer allocated to the first transmission module, and increase an allocation amount of the reception buffer for the first transmission module in a case where the second transmission module has transmitted an acceptance response to the lending request. The second transmission module is configured to: receive the lending request and transmit the acceptance response to the first transmission module based on a use amount of the reception buffer allocated to the second transmission module, and decrease an allocation amount of the reception buffer for the second transmission module when transmitting the acceptance response.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: August 8, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Yuki Yoshida
  • Patent number: 11698632
    Abstract: Provided is a production system including: a first industrial machine configured to control a second industrial machine; and circuitry configured to acquire data relating to an operation of at least one of the first industrial machine or the second industrial machine, wherein the first industrial machine comprises a synchronous area regularly subjected to synchronization and an asynchronous area different from the synchronous area, and wherein the first industrial machine is configured to: write the data into the asynchronous area; and transmit the data written in the asynchronous area to an external device.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: July 11, 2023
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Takeshi Nagata, Takahiko Suzuki
  • Patent number: 11681793
    Abstract: Technologies for memory management with memory protection extension include a computing device having a processor with one or more protection extensions. The processor may load a logical address including a segment base, effective limit, and effective address and generate a linear address as a function of the logical address with the effective limit as a mask. The processor may switch to a new task described by a task state segment extension. The task state extension may specify a low-latency segmentation mode. The processor may prohibit access to a descriptor in a local descriptor table with a descriptor privilege level lower than the current privilege level of the processor. The computing device may load a secure enclave using secure enclave support of the processor. The secure enclave may load an unsandbox and a sandboxed application in a user privilege level of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 20, 2023
    Assignee: INTEL CORPORATION
    Inventors: Michael LeMay, Barry E. Huntley, Ravi Sahita
  • Patent number: 11681533
    Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Ron Gabor, Alaa Alameldeen, Abhishek Basak, Fangfei Liu, Francis McKeen, Joseph Nuzman, Carlos Rozas, Igor Yanover, Xiang Zou
  • Patent number: 11675515
    Abstract: An intelligent data partitioning engine processes instructions to monitor an input queue of a cluster computing framework processing on a distributed computing system. The intelligent data partitioning engine calculates data requirements for processing of one or more program files in the input queue and determines, based on a block size and available processing resources of a plurality of nodes of the distributed computing system, a number of data partitions. Based on the data partitions, the intelligent data partitioning engine triggers execution of the one or more program files by the cluster computing framework, where the cluster computing framework is configured based on the block size and the number of data partitions and updates the data requirements for processing of the one or more program files based on feedback from the cluster computing framework corresponding to one or more previous processing runs of the one or more program files.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: June 13, 2023
    Assignee: Bank of America Corporation
    Inventors: Sheetal Bhatia, Sandeep Kumar Chauhan, Anuranjan Kishore
  • Patent number: 11663168
    Abstract: A server in a cloud-based environment interfaces with storage devices that store shared content accessible by two or more users. Individual items within the shared content are associated with respective object metadata that is also stored in the cloud-based environment. Download requests initiate downloads of instances of a virtual file system module to two or more user devices associated with two or more users. The downloaded virtual file system modules capture local metadata that pertains to local object operations directed by the users over the shared content. Changed object metadata attributes are delivered to the server and to other user devices that are accessing the shared content. Peer-to-peer connections can be established between the two or more user devices. Object can be divided into smaller portions such that processing the individual smaller portions of a larger object reduces the likelihood of a conflict between user operations over the shared content.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: May 30, 2023
    Assignee: Box, Inc.
    Inventors: Ritik Malhotra, Tanooj Luthra, Sri Sarat Ravikumar Tallamraju
  • Patent number: 11640317
    Abstract: Systems and methods are directed to methods and apparatus for transferring ownership of common resources from a source entity, which owns a resource, to a destination entity, which will own the resource, in a distributed system. The method includes the source entity receiving a command to change ownership (the MOVE command), and then marking the source entity as no longer owning the common resource. The source entity then sends a MOVE command to the destination entity, which will then update its common resource ownership table to reflect that the ownership of the common resource has been transferred from the source entity to the destination entity. It is advantageous that the updating of ownership of the common resource in the source entity occur simultaneously with the dispatching of the MOVE command to the destination entity.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 2, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Piyush Patel, Kevin Mann, Theodore Haggis, Malvika Singh, Mit Kutchi
  • Patent number: 11625180
    Abstract: A storage service supports attachment of multiple clients to a distributed storage object and further supports persistent reservations that govern types of access the respective clients are granted with respect to the distributed storage object. In order to efficiently distribute reservation state changes to multiple partitions of the distributed storage object hosted by different data storage units/servers, existing connections are used between the data storage units/servers hosting the partitions of the distributed storage object and the connected clients to propagate reservation state changes.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: April 11, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Swapnil Vinay Dinkar, Pradeep Kunni Raman, David Matthew Buches, Hon Ping Shea, Norbert Paul Kusters
  • Patent number: 11620081
    Abstract: A first block storage server virtual machine to host a first volume using one or more storage devices of a computer system is executed by the computer system. A second virtual machine having access to a virtual block storage device is executed by the computer system. A block storage client is executed by the computer system. A first block storage operation is received by the block storage client from the second virtual machine, the first block storage operation to perform on the virtual block storage device. A message is sent by the block storage client to the first block storage server virtual machine to cause the first block storage server virtual machine to perform the block storage operation with the first volume.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 4, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Anthony Nicholas Liguori, Marc Stephen Olson
  • Patent number: 11609861
    Abstract: A method includes synthetizing a hardware description language (HDL) code into a netlist comprising a first a second and a third components. The method further includes allocating addresses to each component of the netlist. Each allocated address includes assigned addresses and unassigned addresses. An internal address space for a chip is formed based on the allocated addresses. The internal address space includes assigned addresses followed by unassigned addresses for the first component concatenated to the assigned addresses followed by unassigned addresses for the second component concatenated to the assigned addresses followed by unassigned addresses for the third component. An external address space for components outside of the chip is generated that includes only the assigned addresses of the first component concatenated to the assigned addresses of the second component concatenated to the assigned addresses of the third component. Internal addresses are translated to external addresses and vice versa.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 21, 2023
    Assignee: Marvell Asia Pte Ltd
    Inventors: Saurabh Shrivastava, Shrikant Sundaram, Guy T. Hutchison
  • Patent number: 11593157
    Abstract: A method for providing an asynchronous execution queue for accelerator hardware includes replacing a malloc operation in an execution queue to be sent to an accelerator with an asynchronous malloc operation that returns a unique reference pointer. Execution of the asynchronous malloc operation in the execution queue by the accelerator allocates a requested memory size and adds an entry to a look-up table accessible by the accelerator that maps the reference pointer to a corresponding memory address.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 28, 2023
    Assignee: NEC CORPORATION
    Inventor: Nicolas Weber
  • Patent number: 11593547
    Abstract: Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 28, 2023
    Assignee: Xilinx, Inc.
    Inventors: Lucian Petrica, Mario Daniel Ruiz Noguera
  • Patent number: 11586391
    Abstract: A technique efficiently migrates a live virtual disk (vdisk) across storage containers of a cluster having a plurality of nodes deployed in a virtualization environment. Each node is embodied as a physical computer with hardware resources, such as processor, memory, network and storage resources, that are virtualized to provide support for one or more user virtual machines (UVM) executing on the node. The storage resources include storage devices embodied as a storage pool that is logically segmented into the storage containers configured to store one or more vdisks. The storage containers include a source container having associated storage policies and a destination container having different (new) storage policies.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 21, 2023
    Assignee: Nutanix, Inc.
    Inventors: Kiran Tatiparthi, Mukul Sharma, Saibal Kumar Adhya, Sandeep Ashok Ghadage, Swapnil Ingle
  • Patent number: 11580217
    Abstract: Example methods are provided for virtual machine introspection in which a guest monitoring mode (GMM) module monitors the execution of guest calls by an agent that resides in a virtual machine (VM). The GMM module sets a bit in bit mask that corresponds to a guest call that the agent needs to execute, and inserts an invisible breakpoint in the code of the guest call. If the GMM module detects that despite the setting of the bit in the bit mask, the agent does not complete the execution of the code (due to the invisible breakpoint not being triggered), then the GMM module considers this condition as a potential hijack of the VM by malicious code.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: February 14, 2023
    Assignee: VMWARE, INC.
    Inventor: Prasad Dabak
  • Patent number: 11580039
    Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Robert Walker
  • Patent number: 11579788
    Abstract: Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Henry Mitchel, Joe Grecco, Sujoy Sen, Francesc Guim Bernat, Susanne M. Balle, Evan Custodio, Paul Dormitzer
  • Patent number: 11570249
    Abstract: Methods, apparatus, and computer-accessible storage media for providing redundant storage gateways. A client may create a storage gateway group and add storage gateways to the group. The client may assign one or more volumes on a remote data store to each the storage gateways in the group. Volume data for each storage gateway in the group may be replicated to at least one other storage gateway in the group. If one of the gateways in the group becomes unavailable, one or more other gateways in the group may take over volumes previously assigned to the unavailable gateway, using the replicated data in the group to seamlessly resume gateway operations for the respective volumes. Client processes that previously communicated with the unavailable gateway may be manually or automatically directed to the gateway(s) that are taking over the unavailable gateway's volumes.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: January 31, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: James Christopher Sorenson, III, Yun Lin
  • Patent number: 11570121
    Abstract: An apparatus with a data input, a data output, a first buffer, a second buffer, and control logic is disclosed. The control logic is equipped to route data packets that are received through the data input to the first buffer or the second buffer and to flag them as valid or invalid, and to provide data packets that are to be output through the data output from the first buffer or the second buffer, equipped to provide a data packet that is to be output through the data output from the first buffer when the data packet is being written into the first buffer at the time of a start of the readout, to provide it from the second buffer when the data packet is being written into the second buffer at the time of a start of the readout.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 31, 2023
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventors: Frank Quakernack, Daniel Jerolm
  • Patent number: 11551779
    Abstract: An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Harish V. Gadamsetty
  • Patent number: 11544013
    Abstract: An information handling system includes a first storage array having a first logical block table with logical block addresses. Each logical block address includes a pointer to an associated data block in a first storage volume of the first storage array. The second storage array includes a second logical block table having the logical block addresses and a second storage volume. The first storage array receives a data read command from the second storage array to a first logical block address, and in response to the data read command, determines that a data block pointed to by the first logical block address in the first storage array is also pointed to by second logical block address that is adjacent to the first logical block address in the first logical block table, and sends the data block and metadata to the second storage array, the metadata indicating that the second logical block address points to the data block.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Dell Products L.P.
    Inventors: TingWei Wang, Ming Tong, KeCheng Bi
  • Patent number: 11543965
    Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 3, 2023
    Inventors: Sompong Paul Olarig, Son T. Pham
  • Patent number: 11537310
    Abstract: Replication of data from a primary computing system to a secondary computing system. The replication is single-threaded or multi-threaded depending on one or more characteristics of the data to be replicated. As an example, the characteristics could include the type of data being replicated and/or the variability on that data. Also, the multi-threading capabilities of the primary and secondary computing systems are determined. Then, based on the identified one or more characteristics of the data, the primary computing system decides whether to perform multi-threaded replication and the multi-threading parameters of the replication based on the one or more characteristics of that data, as well as on the multi-threading capabilities of the primary and secondary computing system.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 27, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Deepak Verma, Kesavan Shanmugam, Michael Gregory Montwill
  • Patent number: 11537593
    Abstract: A fast-copyable database apparatus includes a processor and a memory in electronic communication with the processor. The memory stores a database table with multiple records each having a compound key including a version identifier. The memory also stores instructions executable to cause the processor to generate a first virtual clone of the database table and a second virtual clone of the database table, receive a query at the first virtual clone, and modify the query so that it includes a version identifier of the first virtual clone. The processor can query the database table using the modified query to generate a response based in part on each record from the set of records having a version identifier associated with an ancestral path of the version identifier of the first virtual clone, and send the response. Each compound key includes a version identifier and a data portion.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 27, 2022
    Assignee: Hedera Hashgraph, LLC
    Inventors: Leemon C. Baird, III, Mance Harmon
  • Patent number: 11531631
    Abstract: The number of QoS group execution IO with respect to a logical device is retained in both of an inter-controller shared memory and an in-controller shared memory. Then, a processor of a storage device compares the number of in-controller execution IO with an update interval threshold value set by the following expression. Update Interval Threshold Value=(“QoS Group IOUpper Limit Value”?(“Number of QoS Group Execution IO” in In-Controller Shared Memory+“Number of In-Controller Execution IO”))דMargin Ratio Coefficient”÷“Number of Controllers in System” Then, the processor adds the number of in-controller execution IO to the number of QoS group execution IO of the inter-controller shared memory when the number of in-controller execution IO is greater than or equal to the update interval threshold value, and performs rewriting in the inter-controller shared memory.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: December 20, 2022
    Assignee: HITACHI, LTD.
    Inventor: Chenqi Zhu
  • Patent number: 11526296
    Abstract: An operation method of a controller for controlling a memory device includes: queuing an identifier of a logical address region associated with a read request from a host in a most recently used (MRU) entry of an internal logical address region queue; increasing a weighted value for a read count of the logical address region by a first value according to whether the identifier of the logical address region has been queued in the logical address region queue before being queued in the MRU entry; adding the weighted value to the read count of the logical address region; providing the host with a map segment corresponding to the logical address region according to a threshold of the read count; and controlling a read operation of the memory device based on a physical address according to whether the read request includes the physical address.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Ho Ryong You, Su Hwan Kim, Seung Hun Kim, Ji Hoon Seok, Young Bin Song, Dong Sun Shin, Jae Yeon Jang
  • Patent number: 11513726
    Abstract: A storage device includes a memory device including a plurality of zones, each of the plurality of zones having a plurality of memory blocks, a buffer memory device including a host buffer receiving write data to be stored in one of the plurality of zones, and a memory buffer temporarily storing the write data transmitted from the host buffer, a buffer controller configured to control the buffer memory device to transmit the write data to the memory device, and a write operation controller configured to control the memory device to store the write data in the one of the plurality of one zones. The write operation controller controls the memory device to obtain the previously stored data and a corrected write data and to store the previously stored data and the corrected write data in a second memory block group after the write operation controller detects an error in the write data.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Jae Youn Jang
  • Patent number: 11494121
    Abstract: A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: November 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yuhwan Ro, Shinhaeng Kang, Seongwook Park, Seungwoo Seo
  • Patent number: 11487906
    Abstract: According to one or more embodiments of the present invention, a computer implemented method includes enabling, by a secure interface control of a computer system, a non-secure entity of the computer system to access a page of memory shared between the non-secure entity and a secure domain of the computer system based on the page being marked as non-secure with a secure storage protection indicator of the page being clear. The secure interface control can verify that the secure storage protection indicator of the page is clear prior to allowing the non-secure entity to access the page. The secure interface control can provide a secure entity of the secure domain with access to the page absent a check of the secure storage protection indicator of the page.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lisa Cranton Heller, Fadi Y. Busaba, Jonathan D. Bradbury
  • Patent number: 11482278
    Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
  • Patent number: 11483400
    Abstract: A computer program product, system, and computer implemented method comprises a multi-layered approach to virtual IP address assignment, where a managing computing node may control the generation of virtual IP addresses and assignment thereof to respective computing nodes, and where each respective computing node can control the allocation and binding of those virtual IP addresses to applications for the virtual IP addresses assigned to that computing node. Furthermore, in some embodiments, the approach includes a process to re-allocate virtual IP addresses to rebalance resources already allocated to a computing node and to address changing conditions.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: October 25, 2022
    Inventors: Ming Zhu, Harsha Kancharthi