Abstract: A method for processing floating point operations in a multi-processor system including a plurality of single processor cores is provided. In this method, upon receiving a group setting for performing an operation, the plurality of single processor cores are grouped into at least one group according to the group setting, and a single processor core set as a master in the group loads an instruction for performing the operation from an external memory, and performs parallel operations by utilizing floating point units (FUPs) of all single processor cores in the group according to the instructions.

Abstract: An apparatus comprises processing circuitry which has a hypervisor execution mode for execution of a hypervisor for managing one or more virtual processors executing on the processing circuitry, and at least one less privileged execution mode than the hypervisor execution mode. In response to a conditional yield to hypervisor instruction executed in the at least one less privileged execution mode, an instruction decoder controls the processing circuitry to determine whether at least one trap condition is satisfied, and when the at least one trap condition is determined to be satisfied, to switch the processing circuitry to the hypervisor execution mode; and store, in at least one storage element accessible to instructions executed in the hypervisor execution mode, at least one item of scheduling hint information for estimating whether the at least one trap condition is still satisfied.

Abstract: The present invention provides an interrupt handling system for handling interrupts in a computer system is provided. The interrupt handling system captures and processes the interrupts in a user space of the computer system. The present invention also provides for an interrupt registration method that facilitates interrupt handling in the user space during porting of user applications from one platform to another.

Abstract: A first processor for executing program code has a control interface mapped to the memory address space of a second processor and provides the second processor with direct mapped access to state information of the first processor. The first processor responds to an exception causing event to enter a halted mode stopping execution of the program code and issuing a trigger event. The second processor responds to the trigger to execute an exception handling routine during which the second processor accesses and modifies the state information via the control interface as required by the exception handling routine. On completion of the exception handling routine, the second processor causes the first processor to exit the halted mode and resume execution of the program code. Thus, the program code is physically separated from the software used to perform the exception handling routine to improve security.

Abstract: Apparatus and methods are disclosed for implementing block-based processors having custom function blocks, including field-programmable gate array (FPGA) implementations. In some examples of the disclosed technology, a dynamically configurable scheduler is configured to issue at least one block-based processor instruction. A custom function block is configured to receive input operands for the instruction and generate ready state data indicating completion of a computation performed for the instruction by the respective custom function block.

Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.

Abstract: An aspect of the present disclosure relates to one or more techniques to identify and resolve storage array errors. In embodiments, an error notification related to a computing device can be received. One or more threads related to the error notification can further be identified. Additionally, an error resolution technique can be performed based on each identified thread.

Abstract: An electronic device includes a power supply circuit, a first counter that counts the number of times that supply of external power to the power supply circuit is stopped, a second counter that is operated by a first power and counts the number of times that generation of the plurality of kinds of power is stopped, a third counter counting the number of times that any of the plurality of kinds of power is dropped to a predetermined voltage or less, a non-volatile first memory storing status information indicating whether or not supply of the external power to the power supply circuit is properly stopped, and a fourth counter that counts the number of times that the supply of the external power to the power supply circuit is properly stopped and the number of times that the supply of the external power to the power supply circuit is abnormally stopped.

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Abstract: The disclosure relates to processing in-flight blocks in a processor pipeline according to an expected execution mode to reduce synchronization delays that could otherwise arise due to transitions among processor modes with varying privilege levels (e.g., user mode, supervisor mode, hypervisor mode, etc.). More particularly, a program counter associated with an instruction block to be fetched may be translated to one or more execute permissions associated with the instruction block and the instruction block may be associated with a speculative execution mode based at least in part on the one or more execute permissions. Accordingly, the instruction block may be processed relative to the speculative execution mode while in-flight within the processor pipeline.

Abstract: Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry (42) responds to a trigger event to enter a real time issue policy mode to control the issue circuitry (22) to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

Abstract: An execution unit is described which is particularly configured to generate an exponential of an operand floating point format. The operand is multiplied by a fixed multiplicand, logged to the base 2 (e) to generate a multiplication result. An integer part and a fractional part are extracted from the multiplication result. An exponent register stores the integer part to form the exponent of the exponential result. A lookup table has a plurality of entries each providing a value of 2f for a fractional part f used to access a lookup table. The fractional part is derived from a mantissa of the operand. That is, first and second bit sequences are extracted from the mantissa. One of the bit sequences is used to generate an estimated fractional component, and the other is used to access a value from the lookup table.

Abstract: Disclosed herein is an apparatus for continuous profiling for a multicore embedded system, the apparatus including a profiling data reception unit for receiving one or more pieces of profiling source data, in which events for each core in a multicore embedded system are written, from the multicore embedded system; a profiling data analysis unit for analyzing the profiling source data, determining a time at which each of events included in the profiling source data occurred and a core corresponding to the event, and determining whether each of the events is a past event depending on the time at which the event occurred; and a profiling file management unit for distinguishing each of the events depending on the determination of whether the event is a past event and storing the events in profiling files.

Abstract: Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction.

Abstract: An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Abstract: Methods, systems and apparatuses for performing walk operations of single instruction, multiple data (SIMD) instructions are disclosed. One method includes initiating, by a scheduler, a SIMD thread, where the scheduler is operative to schedule the SIMD thread. The method further includes fetching, a plurality of instructions for the SIMD thread. The method further includes determining, by a thread arbiter, at least one instruction that is a walk instruction, where the walk instruction iterates a block of instructions for a subset of channels of the SIMD thread, where the walk instruction includes a walk size, and where the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in a walk iteration in association with the walk instruction. The method further includes executing the walk instruction based on the walk size.

Abstract: The disclosed technology is generally directed to microcontrollers. In one example of the technology, an operating system is run on at least one processor of a multi-core controller. At the operating system, a command that is associated with a manufacturer test mode is received. A permission associated with the command is requested. The permission is based, at least in part, on the status of a one-way e-fuse. Responsive to the permission associated with the command being granted, the command is caused to be processed.

Abstract: A facility is provided that, when installed, removes from an architecture a selected architectural function, such that the function is not able to be turned on/off regardless of other controls within the environment. When the facility is installed, the architectural function is not supported when processing in an architectural mode based on the architecture. It is as if the selected architectural function is no longer available in the architecture, and in fact, the code implementing the facility may have been deleted, bypassed, or otherwise eliminated. One such architectural function is virtual address translation, such as dynamic address translation (DAT), and the architecture is, for instance, ESA/390.

Abstract: Method and apparatus are provided for synchronising execution of a plurality of threads on a multi-threaded processor. A program executed by a thread can have a number of synchronisation points corresponding to points where execution is to be synchronised with another thread. Execution of a thread is paused when it reaches a synchronisation point until at least one other thread with which it is intended to be synchronised reaches a corresponding synchronisation point. Execution is subsequently resumed. A control core maintains status data for threads and can cause a thread that is ready to run to use execution resources that were occupied by a thread that is waiting for a synchronisation event.

Abstract: A data processing apparatus and method that relate to the field of communications network technologies are provided which are used to solve a problem of how to reduce power consumption of a UE. In embodiments of the present invention, an acquiring module acquires a first maximum downlink delay tolerance (MDDT) sent by a core network entity, and provides the first MDDT to a determining module, where the first MDDT indicates a maximum delay tolerance value corresponding to processing, by the apparatus, downlink data of all services on the apparatus; the determining module determines time information of a first MDDT timer by using the first MDDT; and a changing module changes a UE status according to the time information of the first MDDT timer determined by the determining module or changes a UE status according to time information of a first IST.

Abstract: Embodiments related to selecting a runahead poison policy from a plurality of runahead poison policies during microprocessor operation are provided. The example method includes causing the microprocessor to enter runahead upon detection of a runahead event and implementing a first runahead poison policy selected from a plurality of runahead poison policies operative to manage runahead poison injection during runahead. The example method also includes during microprocessor operation, selecting a second runahead poison policy operative to manage runahead poison injection differently from the first runahead poison policy.

Abstract: An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.

Abstract: First and second types of vector load instruction are provided. For the first type, a response action is performed when an exceptional condition is detected for a load operation performed for a first active data element of at least one vector register, but when the exceptional condition is detected for an active data element other than the first active data element, the response action is suppressed and element identifying information is stored identifying the element which caused the exceptional condition. For the second type, the response action is suppressed and the element identifying information is stored when the exceptional condition arises for any active data element. This approach is useful for allowing loop speculation and loop unrolling to be used together to improve performance of vectorised code.

Abstract: Examples relate to providing concurrent dead actor collection. In some examples, a blocked notification is received from an actor of a number of actors in a distributed system, where the actors are arranged in an actor hierarchy that describes communication links between the actors. In response to receiving the blocked notification, a blocked status is requested from each other actor in a loop subset of the actors, where each of the other actors is connected to the actor in the actor hierarchy by an incoming edge. After using the blocked status of each of the other actors to determine that incoming edges of the actor refer to blocked actors, the actor is designated for garbage collection.

Abstract: A method, an information handling system (IHS), and an event logging system generate combined event logs in an IHS. The method includes receiving, via a remote access controller (RAC), a tagged log containing operating system (OS) event data. A hardware log containing hardware event data is retrieved from a RAC memory. The tagged log and the hardware log are combined to form a combined event log containing both OS event data and hardware event data in a uniform format. The combined event log is stored to the RAC memory.

Abstract: Embodiments of the invention are directed to methods for handling cache prefetch requests. The method includes receiving a request to prefetch data from main memory to a cache. The method further includes based on a determination that the prefetch request is a speculative prefetch request, determining if the cache is being used for transactional memory. The method further includes based on a determination that the cache is not being used for transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, rejecting the prefetch request.

Abstract: A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.

Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

Abstract: Systems and methods are provided for optimizing power consumption for power line communication (PLC). An example system may include a coupler that connects the system to a power line; an analog front end (AFE) for handling communications over the power line via the coupler; and a processor for controlling power consumption of the AFE. The processor may determine information regarding one or more control parameters of the analog front end (AFE), the information relating to powerline communications (PLC) over the power line; and based on the information, sets or adjusts the one or more control parameters of the analog front end (AFE), to control power consumption of the analog front end (AFE) during the powerline communications (PLC) over the power line. The analog front end (AFE) may then transmit or receive data over the power line using powerline communications (PLC), based on the one or more control parameters.

Abstract: A measurement method, an electronic device, and a measurement system where the electronic device reads, from a hardware storage device, running code and running data that are in a running process of a virtual machine manager (VMM), and generates first verification information according to the running code and the running data, and the electronic device stores the first verification information, and transmits, to a trusted data center, log information generated in a process that is from reading, by the electronic device, the running code and the running data to storing, by the electronic device, the first verification information such that the trusted data center measures the electronic device using the first verification information acquired from the electronic device and second verification information generated according to the log information.

Abstract: Branch prediction is suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions.

Abstract: Systems and methods for contextually allocating emulation resources for providing an emulation session are disclosed. The method involves a plurality of emulation parameters including the computer product to be emulated, context data defining an emulation context, at least one kind of external resource usable to provide the emulation of the computer product. The method includes receiving an emulation request from a client device; determining a required class of service for providing the emulation based on the context data; determining a plurality of possible resource instances providable by the emulator system; selecting at least one selected resource instance from the plurality of possible resource instances to provide an operating instance of the at least one kind of external hardware resource for the emulation based at least in part on the required class of service; and providing the emulation to the client device using the at least one selected resource instance.

Abstract: A computerized method is provided for protecting processes operating within a computing device. The method comprises an operation for identifying, by a virtualization layer operating in a host mode, when a guest process switch has occurred. The guest process switch corresponds to a change as to an operating state of a process within a virtual machine. Responsive to an identified guest process switch, an operation is conducted to determine, by the virtualization layer, whether hardware circuitry within the computing device is to access a different nested page table for use in memory address translations. The different nested page table alters page permissions for one or more memory pages associated with at least the process that are executable in the virtual machine.

Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.

Abstract: Methods and systems for sorting a dataset include partitioning the dataset into 2npartitions, where n is a number of available processors. A first quicksort is performed in parallel across pairs of partitions based on a pivot using a plurality of processors. A second quicksort is performed in parallel on unsorted elements within each partition based on the pivot, where the unsorted elements were left unsorted by the first quicksort. Misplaced elements from a left side of the dataset are swapped with misplaced elements from a right side of the dataset to produce a left dataset that has elements equal to or lower than the pivot and a right dataset that has elements equal to or higher than the pivot.

Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

Abstract: Technologies are generally described for systems, devices and methods effective to implement a virtual machine exit analyzer. A virtual machine handler may receive a request that includes an instruction. The instruction may include a port and a data block identifier. The virtual machine handler may generate a modified request. The modified request may include the port, a block portion identifier and an identification of a comparator. The virtual machine handler may send values identified by the block portion identifier to the comparator. The virtual machine handler may receive an exit indicator from the comparator that indicates whether the virtual machine should exit the core.

Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract: A device generates a model associated with a multi-rate system. The multi-rate system includes a system associated with a clock rate and a sample rate, and the clock rate is greater than the sample rate. The device identifies the clock rate of the multi-rate system based on the model, and identifies a portion, of the model, associated with the sample rate. The device applies clock rate pipelining to adjust the sample rate associated with the portion of the model so that the sample rate substantially equals the clock rate, and generates code associated with the model and the applied clock rate pipelining.

Abstract: The present disclosure provides systems and methods for multi-path rendering on tile based architectures including executing, with a graphics processing unit (GPU), a query pass, executing, with the GPU, a condition true pass based on the query pass without executing a flush operation, executing, with the GPU, a condition false pass based on the query pass without executing a flush operation, and responsive to executing the condition true pass and the condition false pass, executing, with the GPU, a flush operation.

Abstract: The storage section of the multifunction peripheral stores location information containing a storage location of software which transmits a control command whose execution is permissible. The execution permission judging section of the multifunction peripheral includes (I) a storage location detecting section which detects a storage location of software which has participated in a transmission of a received control command and (II) a command permitting/prohibiting section which (i) prohibits execution of the received control command when a storage location indicated by the location information is not detected by the storage location detecting section but (ii) permits execution of the received control command when the storage location is detected by the storage location detecting section.

Abstract: A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises snapshot capture logic that captures snapshots of tagpipe arbs—including information about whether the tagpipe arb is a load, snoop, store or other arb type and whether the tagpipe arb completed or replayed—and a plurality of configurable register modules operable to store user-configured snapshot patterns. Configuration logic enables a user to specify, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect as well as dependencies between the configurable register modules. A register module becomes triggered if a tagpipe arb or pattern of tagpipe arbs meets the user-specified properties for the register module and if any other register module on which the register module depends is also in a triggered state.

Abstract: In some examples, a privileged domain includes a function of a Basic Input/Output System (BIOS). A request to access the function of the BIOS is routed to the privileged domain. The privileged domain determines whether to execute the function based on identifying at least one selected from among a source of the request and a context of the request.

Abstract: A network of sensor and controller nodes having the ability to be dynamically programmed and receive updated software from one another, and from a host system. Each network node includes multiple state machines, at least some of which are operable relative to physical pins at the network node; the physical pins correspond to inputs from sensor functions or outputs to control functions. The network nodes include microcontrollers that are operable in an operating mode to execute a state machine and respond to commands from other nodes or the host, and in a read mode to receive and store program instructions transmitted from other nodes or the host. A learn mode is also provided, by way of which a network node can store program code corresponding to instructions and actions at the node when under user control.

Abstract: System and methods are provided for performing image noise reduction. A pixel having an initial pixel value is selected from an image for performing noise reduction, wherein the image is stored in a data structure in a non-transitory computer-readable storage medium. A block window including a plurality of pixel blocks associated with the selected pixel is determined, wherein a pixel block includes a plurality of pixels. A plurality of pixel block average values for the plurality of pixel blocks are calculated, wherein a pixel block average value corresponds to an average pixel value of a pixel block. A weighted average of the plurality of pixel block average values with respect to the selected pixel is calculated using a bilateral filtering algorithm. The data structure is updated by replacing the initial pixel value of the selected pixel with the weighted average of the plurality of pixel block average values.

Abstract: This follows a data processing system comprising multiple GPUs includes instruction queue circuitry storing data specifying program instructions for threads awaiting issue for execution. Instruction characterization circuitry determines one or more characteristics of the program instructions awaiting issue within the instructional queue circuitry and supplies this to operating parameter control circuitry. The operating parameter control circuitry alters one or more operating parameters of the system in response to the one or more characteristics of the program instructions awaiting issue.