Abstract: A processor includes a prediction engine coupled to a training engine. The prediction engine includes a loop exit predictor. The training engine includes a loop exit branch monitor coupled to a loop detector. Based on at least one of a plurality of call return levels, the loop detector of the processor takes a snapshot of a retired predicted block during a first retirement time, compares the snapshot to a subsequent retired predicted block at a second retirement time, and based on the comparison, identifies a loop and loop exit branches within the loop for use by the loop exit branch monitor and the loop exit predictor to determine whether to override a general purpose conditional prediction.

Abstract: A technique for handling uncorrected memory errors (UEs) inside a kernel text section, the kernel text section being stored in a memory that is operably coupled to a CPU executing kernel program instructions. In an embodiment, a UE is detected that affects the kernel text section. The current instruction affected by the UE is identified. The UE-affected instruction is recovered by loading a copy thereof into the memory from a kernel image maintained in persistent storage. The UE-affected instruction is emulated using the copy of the UE-affected instruction. The instruction pointer of the CPU is then incremented to point to a next instruction in the memory that would normally be executed by the UE-affected instruction had there been no UE.

Abstract: A method of allocating computer resources in a computer system including a multicore processor having a plurality of cores. The method includes monitoring usage of the computer resources by processes executing on the computer system and determining, based upon the monitoring, that one of the processes is a high-utilization process consuming greater than a predefined threshold of the computer resources and corresponds to an application in an interactive state. One or more of the plurality of cores are allocated to the high-utilization process and other of the plurality of cores are allocated to remaining processes, thereby improving performance of the high-utilization process. Upon detecting the application has transitioned from the interactive state, one or more of the cores are previously allocated to the high-utilization process are enabled to be allocated to other than the high-utilization process.

Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.

Abstract: Techniques are disclosed for data integration on retargetable engines in a networked environment. The networked environment includes data processing engines of different types and having different sets of characteristics. A request is received execute a data flow model in the networked environment. The data flow model includes data flow objects. A first data processing engine is programmatically selected based on a predefined set of criteria and the sets of characteristics of the data processing engines. The data flow model is executed using the selected data processing engine and responsive to the request.

Abstract: A parallel processing device includes a processing sequence management unit that reads commands of the command corresponding to a parallel processing start bit to the command corresponding to a parallel processing completion bit from a sequence command storage in sequence to make the sequence command storage output the commands to a first address management unit and a second address management unit, the first address management unit refers to the sequence commands read from the sequence command storage in order from the head to find the command that a first processing execution unit executes, and then instructs the first processing execution unit to execute the command, and the second address management unit refers to the sequence commands read from the sequence command storage in order from the head to find the command that a second processing execution unit executes, and then instructs the second processing execution unit to execute the command.

Abstract: Exclusive access to a core or part of a core, or to multiple cores, but in any case less than all of the cores, of a multiple core processing system. The access can be requested by an instruction, or by a routine. Once granted, the access provides exclusive access to the core so that a program can be run which requires substantially uninterrupted access to the core.

Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

Abstract: Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with minimal power consumption. A plurality of completion signals is received from a processing circuit. Each of the plurality of completion signals identifies an associated operation has been completed by the processing circuit. A plurality of phase signals is generated where the plurality of phase signals includes a respective phase signal generated at a time when each of the plurality of completion signals is expected to be received. A plurality of time differences is determined where each of the time differences is based on a difference between receipt of a completion signal and the respective phase signal generated at the time when the completion signal is expected to be received. A composite difference of the time differences is totaled.

Abstract: Exclusive access to a core or part of a core, or to multiple cores, but in any case less than all of the cores, of a multiple core processing system. The access can be requested by an instruction, or by a routine. Once granted, the access provides exclusive access to the core so that a program can be run which requires substantially uninterrupted access to the core.

Abstract: A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored in the first memory. Access to the bitstream by the first programmable logic device is controlled by the controller. The bitstream is capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with the motherboard using the microprocessor interface.

Abstract: A multithreaded microprocessor includes a thread scheduler and voltage-frequency scheduler (VFS). The thread scheduler uses application-specified QoS requirements, which include required instruction completion rates, and instruction completion information from execution units to schedule the priorities of the threads at which the thread scheduler issues instructions to the execution units. Concurrently, the VFS uses the instruction completion and QoS information to calculate an aggregate utilization of the microprocessor by all the active threads when it is time to scale the voltage-frequency. The aggregate utilization is an effective measure of the amount of work left to be performed relative to the rate requirements. The VFS scales the voltage-frequency based on the aggregate utilization.

Abstract: The time it takes to recover from a system initialization failure may be reduced by determining whether to enable a recovery process immediately, or defer such a process. Sometimes it is desirable to defer a recovery process until certain interdependencies between system components are satisfied.

Abstract: A method for the transmission of digital messages by the output terminals of a monitoring circuit which is integrated into a microprocessor, the digital messages being representative of first specific events which are dependent on the execution of a series of instructions by the microprocessor.

Abstract: Exclusive access to a core or part of a core, or to multiple cores, but in any case less than all of the cores, of a multiple core processing system. The access can be requested by an instruction, or by a routine. Once granted, the access provides exclusive access to the core so that a program can be run which requires substantially uninterrupted access to the core.

Abstract: Methods, apparatus, and products are disclosed for determining when a set of compute nodes participating in a barrier operation on a parallel computer are ready to exit the barrier operation that includes, for each compute node in the set: initializing a barrier counter with no counter underflow interrupt; configuring, upon entering the barrier operation, the barrier counter with a value in dependence upon a number of compute nodes in the set; broadcasting, by a DMA engine on the compute node to each of the other compute nodes upon entering the barrier operation, a barrier control packet; receiving, by the DMA engine from each of the other compute nodes, a barrier control packet; modifying, by the DMA engine, the value for the barrier counter in dependence upon each of the received barrier control packets; exiting the barrier operation if the value for the barrier counter matches the exit value.

Abstract: A system, method and article of manufacture return code management in autonomic systems and more particularly to managing execution of operations in data processing systems on the basis of return code tracking. One embodiment provides a method for managing execution of an operation in a data processing system. The method comprises tracking return codes received from previous executions of the operation in the data processing system, determining an execution behavior of the operation from the tracked return codes, and managing a subsequent execution of the operation on the basis of the determined execution behavior.

Abstract: A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature annotated thereto. An instruction prefetch unit of the processor fetches the stream of grouped instructions from a memory in the processor and an instruction issue logic unit of the processor identifies boundaries between the groups of instructions by executing a signature detection algorithm. In one embodiment, the data processing system includes a pipelined superscalar processor core and is capable of concurrently executing multiple instructions in the same or different pipeline stages.

Abstract: A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences control independently the distributed token via the sequence-net instructions to realize the parallel operating of module. Wherein N flow-sequences is regular type, a new consistency flow-sequence Sc running independently is composed by consistency tokens. The distributed token connecting among multi-machines support the co-operation running among N+1 flow-sequences.

Abstract: The present invention extends to mechanisms for detecting termination and providing information related to termination of a computer system process. A computer system loads a termination function (e.g., an abort, exit, or terminate function) into system memory. The termination function includes termination instructions that, when executed, cause a calling process to terminate without providing information related to a termination event that caused the calling process to terminate. In memory, the functionality of the memory resident termination function is redirected to a memory resident invalid instruction that, when executed, causes an exception providing termination information related to a termination event (e.g., the exception is propagated to an operating system code layer). A memory resident process detects a termination event and the memory resident program calls the termination function.

Abstract: Various systems and methods for error correction of instructions in an instruction cache coupled to a processor are provided. In one embodiment, a plurality of instructions stored in the instruction cache are fetched for execution by the processor, each of the instructions being fetched during a respective one of a plurality of instruction cycles of the processor. Error detection is performed for each of the instructions concurrently with the fetching of a respective one of the instructions.

Abstract: In one embodiment, the invention provides a method for the processing of instructions. A method which comprises analyzing a dynamic execution trace for a program; identifying at least one stream comprising a plurality of basic blocks in the dynamic execution trace; collecting metrics associated with the at least one stream; and optimizing the at least one stream based on the metrics.

Abstract: A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim set from a sequentially accessed memory; selecting a victim way for the selected victim set; reading a next way pointer from a trace line of a trace currently stored in the selected victim way, if the selected victim way has the next way pointer; and writing a next line of the new trace into the selected victim way over the trace line of the currently stored trace. The method also includes forcing a replacement algorithm of next set to select a victim way of the next set using the next way pointer, if the trace line of the currently stored trace is not an active trace tail line.

Abstract: Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address stored in this register. Each processor sends a thread stop notice to a thread controller when the value of its own program counter is coincident with the start address of the forked child thread and ends the execution of a parent thread when receiving a thread end permission from the thread controller.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register.

Abstract: An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an initial instruction that is programmed at a start of the loop, and stores an identification of a different instruction that is programmed between the initial instruction and the particular instruction. According to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, the system initiates an additional fetch of the initial instruction.

Abstract: The present invention provides techniques for retiring instructions that typically complete early as compared to most instructions. In an embodiment, instructions capable of early retirement are processed in accordance with the various processing stages. At a particular stage, if an instruction meets the criteria for early retirement, then that instruction is terminated, e.g., “retired,” and the system is updated to reflect that the instruction has been terminated. However, if the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired.

Abstract: A hazard prediction array consists of an array of saturating counters. The array is indexed through a portion of the instruction address. At issue, the hazard prediction array is referenced and a prediction is made as to whether the current instruction or group of instructions is likely to encounter a flush. If the prediction is that it will flush, the instruction is not issued until it is the next instruction to complete. If the prediction is that the instruction will not flush, it is issued as normal. At completion time, the prediction array is updated with the actual flush behavior. When an instruction is predicted to flush and, thus, not issued until it is the next to complete, the predictor may be updated as if the instruction did not flush.

Abstract: A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.

Abstract: The present invention is characterized by first performing the necessary rendering in the frame period, then during the remaining time of that frame period, rewriting the texture data in the texture buffer memory. The image rendering process for each frame is performed first, then after the rendering process has been completed for the frame, if there is remaining time, that time is used to rewrite the texture data. Therefore, the rendering process is not interrupted, the displayed image is not interrupted or frozen, and it is possible to rewrite the texture data in the small-capacity texture buffer memory and make it possible to use virtually a lot of texture data to render one scene.

Abstract: There is disclosed, for use in a digital signal processor, an apparatus for dynamically sizing a hardware loop that executes a plurality of instruction sequences forming a plurality of instruction loops. The apparatus comprises: 1) N pairs of loop start registers and loop end registers, each loop start register for storing a loop start address and each loop end register for storing a loop end address; 2) N comparators, each of the N comparators associated with one of the N pairs of loop start registers and loop end registers, wherein each of the N comparators compares a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit; and 3) fetch address generation circuitry for detecting the loop start hit and the loop end hit and fetching from an address in a program memory an instruction associated with one of the loop start hit and the loop end hit and loading the fetched instruction into the hardware loop.

Abstract: A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy.

Abstract: A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store an address previously first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run.

Abstract: Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled.

Abstract: A method of reprogramming classification data in a packet classification state machine without interrupting the operation of the state machine is disclosed. Data relating to a plurality of new nodes from a starting node of the classification tree within a classification tree are stored such that they accurately indicate subsequent nodes within the existing data structure. Once the data is stored, a new first node address is stored in a predetermined location. Thereby causing subsequent state machine executions to begin at a new node. The method allows a plurality of state machines to simultaneously use a same classification data memory because the method does not involve overwriting existing data.

Abstract: The present invention provides a stack machine for executing a plurality of instructions one by one. The stack machine comprises an operation folder and an execution unit. The operation folder is used for checking if one or more instructions of a predetermined number of instructions following a specific instruction in a predetermined sequence can be folded with the specific instruction according to a POC folding rule. If they are foldable, these instructions will be combined to form a new instruction. The execution unit is used for executing instructions which cannot be folded by the operation folder or new instructions generated by the operation folder one by one. The instructions are folded to enhance operation efficiency of the stack machine.

Abstract: A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address identifying an entry point address for a corresponding subroutine; and a first table second address identifying a return address of a return for the corresponding subroutine. A second table of entries is also maintained. Each entry in the second table includes: a second table first address identifying a return address of a return for a respective subroutine called by a corresponding subroutine call instruction; a second table second address identifying a target address of the return for the respective subroutine; and a second table third address identifying an entry point address for the respective subroutine. It is determined whether the second table stores an entry whose second table first address corresponds to a return address of a return for a considered subroutine.

Abstract: A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence.

Abstract: A circuit for processing source code with associated array bounds limitations includes an execution unit that generates a register value signal and an index number signal corresponding to an array value defined in a source code instruction. A primary register is connected to the execution unit. The primary register produces a base memory address signal in response to the register value signal. A shadow register is also connected to the execution unit. The shadow register produces an array bound value signal in response to the register value signal. An address computation circuit is connected to the execution unit and the primary register. The address computation circuit generates an effective memory address signal based upon the base memory address signal and the index number signal. An address comparison circuit generates an array bound error signal when an effective memory address associated with the effective memory address signal exceeds an array bound value associated with the array bound value signal.

Abstract: A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.

Abstract: A method for conserving processor registers during the execution of a program in which short term data having a short processing period and long term data having a long processing period are processed. The method includes the acts of: providing a program having a first address space for addressing the short term data and a second address space for addressing the long term data, defining within the processor a first plurality of pooled registers for storing the short term data, executing said program, allocating, responsive to the program, at least one of the pooled registers to the first address space, controlling, via said program, the allocated pool register for the duration of said short processing period, and terminating program control of the allocated pool register upon the expiration of said short processing period.

Abstract: Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table maintains the status of every dispatched instruction as reported by the dispatch unit and the individual execution units. Execution units send finish signals to the completion table responsible for retiring a particular type of instruction. The central completion table retires instructions that may cause an interrupt and instructions whose results may target the same register. The execution units' associated completion tables retire the balance of the instructions and the execution units send instruction status to the central completion table and to each execution unit. This reduces the number of instructions that are retired by the central completion table, increasing the number of instructions retired per clock cycle.

Abstract: An on-chip breakpoint unit of an integrated circuit device is connected to receive the contents of an instruction pointer register via an address communication path. The breakpoint unit has a breakpoint register configured to hold a breakpoint address at which the normal operation of the CPU is to be interrupted for diagnostic purposes, and a comparator circuit operative to compare the breakpoint address with the contents of the instruction pointer register and to issue a breakpoint signal on a breakpoint signal path when there is a match. The on-chip breakpoint unit also has circuitry configured to inhibit generation of the breakpoint signal for a next instruction to be executed upon resumption of normal operation of the CPU after it has been interrupted.

Abstract: A technique for processing register instructions in a pipeline data processor in which multiple instructions may be processed concurrently, and may therefore conflict with one another. Register instructions are identified with register groups indicating which processor registers are affected by the execution of the register instruction. The progress of the execution of the register instruction is then controlled depending upon the identified register groups, in order to avoid conflicts with other concurrently processed instructions.

Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.

Abstract: A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the number of iterations of the loop. The microcode sequence that implements the loop includes a microcode instruction that uses the string count as an operand and/or a result. The microcode instruction unit captures the string count when it is available on either an operand or address bus. The string count is compared to the number of iterations of the string loop to determine when to terminate the microcode loop. If the string count is not captured prior to the microcode instruction unit dispatching more microcode instructions than necessary, the microcode instruction unit notifies other components via a cancel bus. In this manner, the end of a loop is detected prior to the functional unit detecting a mispredicted branch instruction within the microcode loop.

Abstract: A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence.