Using Wired Connections, E.g., Plugboard (epo) Patents (Class 712/E9.002)
  • Patent number: 11909413
    Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventor: Atsushi Kawasumi
  • Patent number: 8954712
    Abstract: Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Monty M. Denneau, Daniel M. Kuchta
  • Patent number: 8332460
    Abstract: A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an input buffer. Copying, in interleaved chunks by the reduction processing cores, contents of the reduction processing cores' input buffers to an interleaved buffer in shared memory; copying, by one of the reduction processing cores, contents of the network write processing core's input buffer to shared memory; copying, by another of the reduction processing cores, contents of the network read processing core's input buffer to shared memory; and locally reducing in parallel by the reduction processing cores: the contents of the reduction processing core's input buffer; every other interleaved chunk of the interleaved buffer; the copied contents of the network write processing core's input buffer; and the copied contents of the network read processing core's input buffer.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blocksome, Daniel A. Faraj
  • Patent number: 8264391
    Abstract: A signal converting system has a multi-segment digital to analog converter coupled to an error shaping loop. A control value is received at a vector processor that indicates a number N of elements that are to be selected from a vector having M elements. The elements of the vector are sorted into a bitonic sequence and separated into a larger value group and a smaller value group using a bitonic split. Only the larger value group is sorted into an ordered sequence with repeated bitonic splits when the control value is less than M/2, and N largest elements are selected from the ordered sequence. Only the smaller value group is sorted into an ordered sequence with repeated bitonic splits when the control value is greater than M/2, and N?M/2 largest elements are selected from the ordered sequence.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Yanto Suryono
  • Patent number: 8095759
    Abstract: A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 10, 2012
    Assignee: Cray Inc.
    Inventors: Dennis C. Abts, Steven L. Scott, Aaron F. Godfrey
  • Patent number: 7865635
    Abstract: A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: January 4, 2011
    Assignee: Fujitsu Limited
    Inventor: Shuichi Yoshizawa