Abstract: Techniques for predictive autoscaling and resource optimization of software deployments. In an implementation, users declare performance objectives, and machine learning of application behavior and load profile is to used to determine minimum cost resourcing to meet the declared performance objectives. In an embodiment, convergent deployments are monitored and related feedback is provided to improve forecasting, behavior modeling, and resource estimation over time.

Abstract: An information processing apparatus includes a processor configured to, when connected devices whose number is greater than a predetermined number are connected to the information processing apparatus, the predetermined number indicating the maximum number of devices simultaneously supplied with power, switch a power supply destination between the connected devices so as to obtain a state in which the number of connected devices simultaneously supplied with power is equal to or less than the predetermined number.

Abstract: The technology described herein is directed towards optimizing power consumption of devices, e.g., in a datacenter. A modified (two-tier) genetic algorithm performs a carbon footprint-based optimization in a first tier to determine a candidate range of coefficients for each device type, e.g., servers, switches and storage devices/systems that likely reduce carbon footprint of each device type. In a second tier of the genetic algorithm, those ranges of coefficients are used in conjunction with actual power usage-based carbon footprint scores of individual devices to find respective sets of coefficients that minimize respective objective functions for the servers, the switches and the storage devices. The sets of coefficients can be used for power capping the devices. Device performance constraint-based intelligent selection can be used in one or both tiers to speed up convergence.

Abstract: The disclosed Security Hardware/Software simultaneously triggers a mild yet effective shock to the invader's fingers, while completely shutting down the device that is being targeted for hacking. A first system interrupt based on a first unsuccessful login into the computer system, and configured to display a warning message to a user on a screen in communication with a keyboard of the computer system. The deterrent shock is delivered to the user based on the first system interrupt. A second system interrupt based on a second unsuccessful login, and configured to trigger an alarm and lock down computer system devices and inform a law enforcement agency of the second system interrupt. A third system interrupt is based on a third unsuccessful login. The third system interrupt is configured to accept a secure pass code from a vendor of the system to restore the system to a preinterrupt condition.

Abstract: A fan control system for use in a server system is disclosed. The fan control system includes a first monitoring and protection chip, a second monitoring and protection chip, a switch, a plurality of fans and a complex programmable logic device (CPLD). In a shutdown state of the server system, the switch is switched under control of the CPLD so that the fans are connected to the second monitoring and protection chip, receive standby power therefrom and run at a standby power level. When the server system is switched to a working state, the switch is switched under control of the CPLD so that the fans are connected to the first monitoring and protection chip, receive operating power therefrom and run at a higher working power level. This design can address different heat dissipation needs of various applications.

Abstract: A power supply apparatus, including: a first power supply component, a power over Ethernet (POE) component, a second power supply component, a first controller, and a power supply path management component. The first power supply component is respectively connected to the first controller and the power supply path management component, the POE component is connected to the first controller, and the first controller and the second power supply component are respectively connected to the power supply path management component. The first controller is configured to: detect whether the first power supply component supplies power; close a power supply path of the POE component when the first power supply component supplies power normally; and control the power supply path management component to open a power supply path of the second power supply component when the POE component supplies power abnormally and the first power supply component does not supply power.

Abstract: A main circuit includes a switching element, and converts electric power input to the main circuit and supplies a result of the conversion to a load. The controller switches a control scheme of the main circuit from a first control scheme to a second control scheme at a first time point when the output value starts to vary and switches the control scheme of the main circuit from the second control scheme to the first control scheme at a second time point when a determination is made that switching of a variation direction of the output value will occur on the basis of a detection value of the detector.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.

Abstract: A method for managing a battery to perform a final action, the method includes determining a battery supplying power to an electronic device is discharging and receiving battery specification information for the battery. The method includes receiving environmental condition information for the battery and determining an open circuit voltage for the battery. The method includes determining a base capacity for the battery, a first capacity reduction for the battery based on the battery specification, and a second capacity reduction for the battery based on the environmental condition information. The method includes determining an overall expected capacity for the battery based on the first capacity reduction and the second capacity reduction, where the overall expected capacity represents available energy. Responsive to determining the available energy for the battery is less than a required energy to perform an action prior to battery depletion, the method includes sending a warning notification.

Abstract: An integrated circuit (IC) device includes a non-volatile memory device with an array of non-volatile memory cells, and an isolation circuit configured to conduct voltage from an internal voltage supply to one of the memory cells during a hidden write operation to the one of the memory cells, and conduct voltage from an external voltage supply to the one of the memory cells during a non-hidden write operation to the one of the memory cells. Current at the external voltage supply can be monitored external to the IC device during the non-hidden write operation, and current of the internal voltage supply is provided by a capacitor that cannot be monitored external to the IC device during the hidden write operation.

Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: An audio activity detector device is disclosed. The audio activity detector device comprises a closed loop feedback regulating circuit that supplies an input signal representative of a time-varying voltage signal to a quantizer circuit, wherein the quantizer circuit, as a function of the input signal, converts the input signal to a quantizer discrete-time signal; a first circuit that, as a function of the discrete-time signal, determines a key quantizer statistic value for the quantizer discrete-time signal; and a second circuit that, as a function of the key quantizer statistic value, determines a signal statistic value for the input signal and a gain control value.

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Abstract: An embodiment of the present invention provides a load sharing control device included in each of multiple power supply devices connected to a load in parallel, the load sharing control device comprising: a first control unit for generating a first control signal which controls an output current of a power supply device, by using the output current of the power supply device and a current of a load share bus; and a second control unit for generating a second control signal which controls an output voltage of the power supply device, by using a target voltage of the power supply device, a feedback voltage received as feedback from the output voltage of the power supply device, and a control voltage according to the first control signal of the first control unit, wherein the first control unit generates the first control signal so that the output current is identical to the current of the load share bus, and limits the output current to a threshold current or less.

Abstract: A method for evaluating metrics associated with isolated execution environments utilized for synthetic monitoring of a web application and modifying the quantity of isolation execution environments hosted by a particular hosting service at a particular geographic location based on the metrics. The method can include receiving an instruction to monitor computing resources at the particular geographic location; obtaining configuration data for the particular geographic location; communicating a request to the particular hosting provider for an identification of a collection of isolated execution environments that are instantiated at the particular geographic location; obtaining metrics associated with the collection of isolated execution environments; evaluating the metrics against the set of scaling criteria; and/or generating an instruction for the particular hosting provider to modify the quantity of the collection of isolated execution environments.

Abstract: A method includes receiving data characterizing a time-dependent first sensor data detected by a first sensor, a time-dependent second sensor data detected by a second sensor, a time-dependent third sensor data detected by a third sensor, a first set of threshold values associated with the first sensor, a second set of threshold values associated with the second sensor, and a third set of threshold values associated with the third sensor and a time window. The first, second, and third sensors are located in a first space of a building. The method further includes calculating a first performance index, a second performance index, and a third performance index. The method also includes classifying the first performance index, the second performance index, and the third performance index into one of a plurality of performance indicators. The method further includes assigning a performance rating score for a space based on the classification.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

Abstract: A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.

Abstract: A seismic sensor assembly can include a housing that defines a longitudinal axis; a sensor; sensor circuitry operatively coupled to the sensor; and overvoltage protection circuitry electrically coupled to the housing.

Abstract: A computing device is provided, including a battery, a processor configured to receive electrical power from the battery via a voltage regulator, and one or more additional electronic components configured to receive electrical power from the battery. The computing device may further include a first current detector configured to detect a total battery discharge current. The voltage regulator may be configured to receive a first analog current signal from the first current detector, convert the first analog current signal into first digital current data, and transmit the first digital current data to the processor. The processor may be further configured to determine a difference between the total battery discharge current and an available electric current limit for the battery. In response to at least determining the difference, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

Abstract: An information handling system includes a Unified Extensible Firmware Interface (UEFI) and a management controller. The management controller establishes a communication channel with the UEFI, and provides a memory path associated with a driver associated with an operation to be performed in the UEFI. Based on the memory path, the UEFI receives the requested driver from a memory associated with the UEFI, and loads the requested driver. The UEFI executes the loaded requested driver, and provides an execution status for executed driver to the management controller.

Abstract: A method of controlling a microgrid comprises receiving, by a power management system, PMS, of the microgrid, operating point values for a plurality of controllable assets. The method comprises determining, by the PMS, an asset headroom. The method comprises determining, by the PMS, a modified operating point value that is dependent on the received operating point value of the controllable asset, the determined asset headroom of the controllable asset, and a total power offset of the microgrid. The method comprises controlling, by the PMS, the controllable assets for which the modified operating point values have been determined in accordance with the modified operating point values.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.

Abstract: Techniques discussed herein can facilitate power management at a User Equipment (UE) via selection of a power management stage based on a current power status. One example aspect is a UE comprising one or more processors configured to: monitor a temperature of the UE via one or more temperature sensors and a power usage of the UE; determine a power status of the UE based at least in part on the temperature of the UE and the power usage of the UE; select, based at least in part on the determined power status, a power management stage of a plurality of power management stages; and implement one or more power management techniques associated with the selected power management stage. A notification can be triggered to alert a user that the processor is implementing the one or more power management techniques prior to implementation.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: A method of power management for a hub having a plurality of Universal Serial Bus (USB)-C ports includes: allocating a guaranteed power budget to each USB-C port of the hub, wherein one of the USB-C ports has a higher power priority and the other USB-C ports have a lower power priority; reducing the guaranteed power budget allocated to a USB-C port with the lower power priority if measured power for that USB-C port is below its currently guaranteed power budget by a predetermined amount; and offering additional power budget to the USB-C port with the higher power priority if the guaranteed power budget allocated to a USB-C port with the lower power priority was previously reduced. Corresponding USB-Power Delivery (PD) integrated circuit (IC) controllers and hubs are also described.

Abstract: A system and/or method can include power of Ethernet (PoE) controller including a PoE interface, a device interface and a controller, communicatively coupled to the PoE interface and the device interface. The controller can be configured to receive device control information via the PoE interface and to generate control instructions in response to the device control information for the device interface.

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a base station, configuration information indicating a set of component carriers (CCs) associated with the UE. The UE may receive, from the base station, a message that activates or deactivates one or more CCs of the set of CCs. The UE may communicate, with the base station, after receiving the message, using one or more activated CCs of the set of CCs over a tuned radio frequency (RF) bandwidth that is based on receiving the message and based on the one or more activated CCs. Numerous other aspects are provided.

Abstract: An information handling system may include a host system, a management controller configured to provide out-of-band management of the information handling system, and a network interface controller including a network interface controller storage resource. The management controller may be configured to: receive, from the host system, a first identifier that is specific to an operating system (OS) of the host system; compare the first identifier to a second identifier provided by the network interface controller, wherein the second identifier is specific to an OS of the network interface controller that is stored on the network interface controller storage resource; and in response to a mismatch between the first identifier and the second identifier, prevent the network interface controller from operating.

Abstract: An information processing apparatus includes a processor connected to a programmable logic circuit. The processor is configured to: allow a first circuit reconfigured in a first region of the programmable logic circuit to execute a process; in parallel with the process of the first circuit, allow a second circuit to be reconfigured in a second region different from the first region; and adjust at least one of a clock frequency used in the process of the first circuit and a clock frequency used in reconfiguration of the second circuit so that a time point at which the process of the first circuit is completed and a time point at which the reconfiguration of the second circuit is completed will become closer to each other.

Abstract: A method for measuring flicker fusion threshold. Set a measurement scheme, including setting N 8-shaped digital frames in a background light area that flickers within a set frequency. Set ten groups of different frequency combinations being applied to the N 8-shaped digital frames. Assign each frequency in each group of the frequency combinations with a stroke of the 8-shaped digital frame. Randomly select, for each of the N 8-shaped digital frames, one from the ten groups of the frequency combinations. Determine the value of each frequency in each group of frequency combinations in the N groups of frequency combinations. Recognize, by the subject, the flickering digits on the N 8-shaped digital frames in the background light area within the set frequency range. Determine the range of the flicker fusion threshold or the final flicker fusion threshold of the subject according to the result that can be seen by the subject.

Abstract: An electronic apparatus includes: a plurality of input ports to which a plurality of first external devices are connected; a converter; an output port to which a second external device is connected; and a processor that controls the converter to convert a plurality of input voltages of the plurality of first external devices connected to the plurality of input ports into an output voltage, identifies whether power is capable of being supplied by each of the input voltages, and controls the converter to output the converted output voltage to the second external device to the output port, based on whether the power is capable of being supplied.

Abstract: In some examples, an electronic device comprises a battery; a storage device storing a user profile, the user profile comprising a usage pattern of the battery; and a processor coupled to the battery and the storage device, the processor to: receive a battery measurement of the battery and operational data of a first component of the electronic device; calculate a battery consumption of the first component based on the battery measurement; compare the battery consumption to the usage pattern; update, based on the comparison, the user profile using a time series model, wherein inputs to the time series model include the battery measurement and the operational data; and adjust a battery consumption of the electronic device based on the updated user profile.

Abstract: Systems and methods for managing temperatures of wearable device components are disclosed. In one aspects, a method includes determining a temperature of an electronic component of the wearable device, determining a rate of temperature change of the electronic component, and determining whether to increase or decrease a transmission rate limit of the electronic component based on the temperature and the rate, adjusting the transmission rate limit based on the determination, and limiting a rate of transmission of the electronic component based on the adjusted transmission rate limit.

Abstract: The present invention suppresses an increase in processing time and power consumption that is associated with function implementation. An electronic device according to an embodiment comprises: an imaging unit (11) that generates image data; a processing unit (14) that executes neural network calculation model-based processing with respect to image data-based data that is read out from the imaging unit; a function execution unit (12) that performs a predetermined function on the basis of the results of the processing; and a detection unit (32) that detects displacement, wherein the processing unit executes the processing when the detection unit detects displacement.

Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.

Abstract: A system, method, and apparatus of power management for computing systems are included herein that optimize individual frequencies of components of the computing systems using machine learning. The computing systems can be tightly integrated systems that consider an overall operating budget that is shared between the components of the computing system while adjusting the frequencies of the individual components. An example of an automated method of power management includes: (1) learning, using a power management (PM) agent, frequency settings for different components of a computing system during execution of a repetitive application, and (2) adjusting the frequency settings of the different components using the PM agent, wherein the adjusting is based on the repetitive application and one or more limitations corresponding to a shared operating budget for the computing system.

Abstract: According to one embodiment, a memory system connectable to a host via each of a first bus and a second bus includes a nonvolatile memory and a controller. The controller stores first data that is necessary for responding to a management command for acquiring a status of the memory system in a first volatile memory before causing the memory system to transition to a low power mode. The controller causes the memory system to transition to the low power mode by stopping supply of power to each of components of the controller except for a first interface circuit connected to a first bus, a second interface circuit connected to a second bus, and the first volatile memory, and stopping the supply of power to the nonvolatile memory.

Abstract: An electronic device and method are disclosed. The electronic device includes a communication circuit, a sensor circuit, a digitizer panel, and a processor. The processor implements the method, including: detecting whether an electronic pen is detached from the electronic device via the sensor circuit, activating the digitizer panel based on detecting detachment of the electronic pen from the electronic device, identifying a state of the electronic pen through a communication linkage with the electronic pen via the communication circuit, and deactivate the activated digitizer panel based on the identified state of the electronic pen.

Abstract: There is provided an apparatus, said apparatus including circuitry for operating in a first discontinuous reception mode including at least one awake period and at least one sleep period, receiving, during operation in the at least one awake period, a first indication from a network to perform at least one of pausing operation of the first discontinuous reception mode such that the apparatus continues operation in the at least one awake period and disabling operation of the first discontinuous reception mode such that the apparatus continues operation in a second discontinuous reception mode.

Abstract: An electronic device includes: a plurality of connection ports to which external devices are able to be connected; and a controller configured to control whether or not to supply power to an external device connected to a connection port in preference to an external device connected to another connection port on the basis of a priority level assigned to each of the plurality of connection ports.

Abstract: Apparatuses and methods for providing resources are provided that include receiving power statuses of resources of a system capable of providing the resources; quantifying the power statuses of the resources; calculating an available soft capacity of the system based on the quantified power statuses and a total capacity of the system; and providing an assigning amount of the resources beyond the calculated available soft capacity to one or more users.

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).

Abstract: A method that may be used for power-over-Ethernet includes generating and sending a first pulse of a voltage signal during a classification phase, receiving a current that is responsive to the first pulse, and determining a nominal power of a powered device (PD) from the current. The method also includes generating and sending a quantity of pulses of the voltage signal subsequent to the first pulse during the classification phase, the quantity of pulses including a command to operate the PD at less than the nominal power level during an operational phase subsequent to the classification phase.

Abstract: The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wiring, and a case where it is preferable to connect the common signal terminals or the power supply terminals by circuits insulated from each other. The counter unit (10) is provided with a switching unit (15) that performs switching between a non-insulated circuit (16) that connects a plurality of common signal terminals (COMA, COMB, COMC) and/or a plurality of power supply terminals (IOV, IOG) by common wiring, and an insulated circuit (17) that connects the plurality of common signal terminals and/or the plurality of power supply terminals by circuits insulated from each other.

Abstract: A mobile terminal (1), a switch control method, and a computer readable storage medium. The mobile terminal (1) comprises a hardware security processor (11), a first information input device (12), and a control switch (14); when the control switch (14) is turned on, if first security information currently collected by the first information input device (12) does not match second security information stored in a storage module, or the second security information does not exist in the storage module when the first security information currently collected by the first information input device (12) is obtained, the hardware security processor (11) controls the control switch (14) to be turned off, so as to prevent a second information input device (15) of the mobile terminal (1) from uploading the collected information to a main processor (16) of the mobile terminal (1).