Clock Control Of Data Processing System, Component, Or Data Transmission Patents (Class 713/600)
  • Patent number: 11907744
    Abstract: In one embodiment, a processor comprises: a first configuration register to store quality of service (QoS) information for a process address space identifier (PASID) value associated with a first process; and an execution circuit coupled to the first configuration register, where the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, insert the QoS information and the PASID value into the command data, and send a request comprising the command data to a device coupled to the processor, to enable the device to use the QoS information of a plurality of requests to manage sharing between a plurality of processes. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Sanjay K. Kumar, Philip Lantz, Gilbert Neiger, Rajesh Sankaran, Vedvyas Shanbhogue
  • Patent number: 11869625
    Abstract: A data transmission circuit and method, and a storage device are provided. The data transmission circuit includes a serial-parallel conversion module, a comparison module, a data conversion module and a write circuit module. The serial-parallel conversion module receives a plurality of pieces of external data in batches and outputs initial parallel data according to the external data. The comparison module compares the received initial parallel data with global data to output a comparison result. The data conversion module, responsive to that the comparison result indicates that the preset threshold is exceeded, inverts the initial parallel data and transmits the inverted data to a data bus, and responsive to that the comparison result indicates that the preset threshold is not exceeded, transmits the initial parallel data to the data bus. The write circuit module transmits data on the data bus to a global data bus.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 11868172
    Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: January 9, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Zhihan Zhang, Yuan Zhang
  • Patent number: 11860597
    Abstract: A smart switch system comprising one or more switching devices. Each one of the switching devices include a first pin, a second pin, a current indication pin, a system current limit pin and a power switch for electrically coupling the first pin to the second pin when the power switch is turned on. Each switching device may adaptively adjust an operation current limit value of the switching device based on a system total current limit value received or set at the system current limit pin and a system current indication signal received at the current indication pin.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: January 2, 2024
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Xingwei Wang, Cheng-Chung Yang, I-Fan Chen, Xiuhong Guo
  • Patent number: 11861230
    Abstract: An operating method of a controller that controls a memory device includes initializing a clock frequency set corresponding to clock signals provided to a plurality of operation modules included in the controller when a change in a current performance or a change in a host request pattern is detected, determining a target performance on the basis of the current performance given after the clock frequency set is initialized, determining an optimal clock frequency set, in which the current performance is able to be maintained equal to or greater than the target performance, by repeatedly performing an operation of changing at least one clock frequency included in the clock frequency set and an operation of monitoring the current performance given after the clock frequency is changed, and providing the plurality of operation modules with clock signals according to the optimal clock frequency set.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Kyeong Seok Kim, Jin Soo Kim, Su Ik Park, Yong Joon Joo
  • Patent number: 11856364
    Abstract: A microphone array system, comprises N microphones, including a first microphone . . . a Nth microphone, wherein N is a natural number greater than 2. Each of the N microphones is provided with: an acoustic transducer for picking up a sound signal and converting the sound signal into an electric signal; a voice activation detector, connected to a corresponding acoustic transducer, and configured to perform a voice activation detection on the electric signal and form an activation signal; a buffer memory, connected to the acoustic transducer, and configured to store a 1/N electric signal of a predetermined segment; a sound wire interface, connected to a corresponding acoustic transducer, the buffer memory, and the voice activation detector, wherein the sound wire interface is connected to an external master chip via a sound wire bus for outputting the activation signal to the external master chip.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 26, 2023
    Assignee: ZILLTEK TECHNOLOGY CORP.
    Inventor: Jinghua Ye
  • Patent number: 11747987
    Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 5, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Fu-Jen Shih, Chia-Ching Huang
  • Patent number: 11736108
    Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: August 22, 2023
    Assignee: Faraday Technology Corp.
    Inventors: Ko-Ching Chao, Chih-Hung Wu, Po-Wen Hsiao, Zhou-Lun Liou
  • Patent number: 11704086
    Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 18, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Sharon Graif, Jason Gonzalez
  • Patent number: 11698673
    Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Binata Bhattacharyya, Paul S. Diefenbaugh
  • Patent number: 11681648
    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: June 20, 2023
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Patent number: 11657610
    Abstract: To provide an I/O signal information system in which a monitoring target portion and I/O signal information are automatically associated with each other and displayed on a display screen when monitoring a facility including a robot. An object identification unit identifies an object based on a correlation between a change of an actual photographed image displayed on a display device by actual photographed data supplied from an imaging device and a change of I/O signal information, and a display control unit causes the display device to display an augmented reality image in a display form in which an image of the I/O signal information has a specific relationship with an image of the object identified.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: May 23, 2023
    Assignee: FANUC CORPORATION
    Inventor: Keisuke Nagano
  • Patent number: 11650851
    Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Stephen T. Palermo, Nikhil Gupta, Vasudevan Srinivasan, Christopher MacNamara, Sarita Maini, Abhishek Khade, Edwin Verplanke, Lokpraveen Mosur
  • Patent number: 11640828
    Abstract: The present application discloses a DECT base station, mobile terminal and system for transmitting data frame. The DECT base station comprises the first codec module and the first RF module. The first codec module is configured to store the acquired encoded data frame in the encoding buffer area of the first codec module; wherein, between the length of the encoded data frame and the length of a B-field data in the TDMA frame, there is a multiple relationship. The first RF module is configured to send, when receiving the first trigger signal, the encoded data frame in the encoding buffer area to mobile terminal. The present application can transmit data frame under the action of the trigger signal, to ensure the completeness and effectiveness of the data frame, thereby increasing the number of broadband voice communication channels.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: May 2, 2023
    Assignee: YEALINK (XIAMEN) NETWORK TECHNOLOGY CO., LTD.
    Inventors: Wanjian Feng, Zhipeng Lin
  • Patent number: 11640836
    Abstract: A system and method are directed to providing a configurable timing control of a memory system. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flipflops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 2, 2023
    Assignee: Rambus Inc.
    Inventors: Michael L. Takefman, Maher Amer, Claus Reitlingshoefer, Riccardo Badalone
  • Patent number: 11567527
    Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 31, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Anand Kumar G
  • Patent number: 11470303
    Abstract: The inventive method involves receiving as input a representation of an ordered set of two dimensional images. The ordered set of two dimensional images is analyzed to determine at least one first view of an object in at least two dimensions and at least one motion vector. The next step is analyzing the combination of the first view of the object in at least two dimensions, the motion vector, and the ordered set of two dimensional images to determine at least a second view of the object; generating a three dimensional representation of the ordered set of two dimensional images on the basis of at least the first view of the object and the second view of the object. Finally, the method involves providing indicia of the three dimensional representation as an output.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: October 11, 2022
    Inventor: Steven M. Hoffberg
  • Patent number: 11460879
    Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: October 4, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden, Xiuting Kaleen C. Man, Gokul Subramani Ramalingam Lakshmi Devi, Xiaojie He
  • Patent number: 11404104
    Abstract: A semiconductor memory device includes: a memory cell array including banks; a command/address buffer receiving a command/address based on a system clock; a data input/output circuit inputting/outputting data based on a data clock; a mode control circuit generating mode selection signals indicating different latencies according to a burst length signal and operation information on a first operation mode differentiated based on a ratio of the data clock to the system clock, and a second operation mode differentiated based on a bank mode; and a latency setting circuit setting a latency according to an activated one of the mode selection signals, generating an internal write command by delaying a write command at least by the set latency according to the system clock during a write operation, and generating an internal read command by delaying a read command by the set latency according to the system clock during a read operation.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 2, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11380413
    Abstract: The present disclosure provides a test system and a test method. The test system includes: a signal providing module, configured to provide a first clock signal and a second clock signal for a to-be-tested memory, the to-be-tested memory executes a write command based on the first clock signal, so that the to-be-tested memory stores preset data, and the to-be-tested memory executes a read command based on the second clock signal, to read storage data stored in the to-be-tested memory; and one of the first clock signal and the second clock signal is a symmetrical clock signal, and the other is an asymmetrical clock signal with a preset duty cycle; and a processing module, configured to obtain the storage data, and obtain a clock signal tolerance of the to-be-tested memory according to a comparison result between the storage data and the preset data.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: July 5, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: YiFei Pan
  • Patent number: 11360919
    Abstract: A data processing system includes a controller configured to control data input/output for a memory according to a request of a host. The controller may include a buffer memory including a plurality of buffers configured to store data transmitted from the memory, a processor group including a plurality of cores respectively connected to the plurality of buffers, each core configured to read respective data from its respective buffer and perform computation using the read data, and a speed control component configured to adjust an operating speed of the processor group based on an amount of unread data of each buffer corresponding to each of the plurality of cores.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventor: Joo Young Kim
  • Patent number: 11277420
    Abstract: Systems and methods implemented by a computer to detect abnormal behavior in a network include obtaining Performance Monitoring (PM) data including one or more of production PM data, lab PM data, and simulated PM data; determining a model based on machine learning training with the PM data; receiving live PM data from the network; utilizing the live PM data with the model to detect an anomaly in the network; and causing an action to address the anomaly.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: March 15, 2022
    Assignee: Ciena Corporation
    Inventors: David Côté, Merlin Davies, Olivier Simard, Emil Janulewicz, Thomas Triplet
  • Patent number: 11270089
    Abstract: The present disclosure discloses an electronic work card, a control method and device thereof, a storage medium and an attendance management system. The electronic work card includes: a controller and a Radio Frequency Identification (RFID) device; wherein the RFID device is configured to identify at least one actuator in the environment, receive the identification information provided by the at least one actuator when the at least one actuator is identified, and send the trigger information to the controller; the controller is configured to obtain the identification information of the actuator after receiving the trigger information of the actuator, determine whether the electronic work card is in the preset workplace according to the identification information, and in response to determining that the electronic work card is not in the preset workplace, control at least part of the functions of the electronic work card to enter the non-working state.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 8, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Xinyi Cheng
  • Patent number: 11263114
    Abstract: Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Douglas Griffith, Emmanuelle Samir Hanna Matta, Evelyn Tingmay Yeung, Srinivasa Rao Muppala
  • Patent number: 11238003
    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 1, 2022
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Patent number: 11199895
    Abstract: In one embodiment, a method receives data regarding processing of a workload by a processor. The data is input into a prediction engine configured to classify the data into a plurality of workload classifications. Each workload classification describes different temporal behavior of the workload. Then, the method outputs a prediction for at least one of the plurality of workload classifications, wherein the prediction is used to control performance of the processor in an upcoming period of time.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Kam-shing Leung, James Hermerding, II, Muhammad Abozaed, Gilad Olswang, Moran Peri, Ido Karavany, William Freelove, Sudheer Nair, Tahi Hollander, Avishai Wagner
  • Patent number: 11171657
    Abstract: A phase and amplitude controlled oscillation device is configured in such a manner that a first controller and a second controller control a phase of a combined output wave obtained by a combiner by performing control to shift phases of respective oscillation frequencies of a first oscillator and a second oscillator in the same direction, and control an amplitude of the combined output wave obtained by the combiner by performing control to shift the phases of the respective oscillation frequencies of the first oscillator and the second oscillator in opposite directions.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: November 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masaomi Tsuru
  • Patent number: 11106392
    Abstract: A data processing system includes: a host suitable for generating an initialization command and generating program mode information by selecting a program mode; a memory device including a plurality of memory cells storing a single level data and a multiple-level data; and a controller suitable for: receiving the initialization command and the program mode information from the host; controlling the memory device to perform an initialization operation on the memory device in response to the initialization command; and controlling the memory device to perform a program operation on the memory device based on the program mode information after the initialization operation is performed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11074169
    Abstract: The present disclosure includes apparatuses, electronic device readable media, and methods for memory controlled data movement and timing. A number of electronic device readable media can store instructions executable by an electronic device to provide programmable control of data movement operations within a memory. The memory can provide timing control, independent of any associated processor, for interaction between the memory and the associated processor.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 11036268
    Abstract: Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 15, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Mudit Srivastava, Abreham Delelegn
  • Patent number: 11022637
    Abstract: A sensor system includes a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed includes determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed is based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 1, 2021
    Assignee: ARM LIMITED
    Inventors: Subbayya Chowdary Yanamadala, Mikael Yves Marie Rien
  • Patent number: 11003609
    Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Fred Worley, Harry Rogers, Sreenivas Krishnan, Zhan Ping, Michael Scriber
  • Patent number: 10969855
    Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 6, 2021
    Inventors: Hyo-Sang Jung, Sang-Wook Ju, Jung-Hun Heo
  • Patent number: 10937473
    Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita
  • Patent number: 10915490
    Abstract: Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Neven Klacar, Murali Krishna, Arunn Coimbatore Krishnamurthy, Jitendra Prasad, Jean-Marie Quoc Danh Tran
  • Patent number: 10908907
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • Patent number: 10904453
    Abstract: Examples embodiments of a method and system for synchronizing active illumination pulses in a multi-sensor imager is provided. Example embodiments of the method disclosed herein include the provision of an illumination pulse for each of N sensors, each of N illumination pulses are set to have the same pulse period and active pulse width. Moreover, example embodiments include setting the active width pulse for each of the N illumination pulses to have maximum exposure time for each of N image sensors, and in further examples, ensuring that the time to capture a frame plus the time interval between subsequent image captures is the same for each sensor. In yet further examples, an offset period between subsequent frame synchronous signals is determined. In yet further example embodiments, an interval between frame captures is adjusted and a negative edge of the frame synchronous signal and an illumination pulse is aligned.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 26, 2021
    Assignee: Hand Held Products, Inc.
    Inventors: Feng Chen, Jie Ren, Haiming Qu, Qing Zhang
  • Patent number: 10833707
    Abstract: Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glenn Gilda, Arthur O'Neill
  • Patent number: 10827424
    Abstract: The present disclosure relates to a mobile terminal in which a clock frequency of a memory varies as needed and a control method thereof, and the mobile terminal may include a memory provided with a table comprising information on a memory clock frequency corresponding to a different multiple of a preset source clock frequency, and a controller configured to primarily change the memory clock frequency of the mobile terminal to any one of frequencies according to the table in accordance with at least one of functions or applications carried out in the mobile terminal, wherein when the memory clock frequency is primarily changed, the controller secondarily changes the changed memory clock frequency to a frequency different from the changed memory clock frequency according to whether or not the communication performance of the mobile terminal is degraded.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Seungkeun Oh, Junsu Park, Jehyun Baek
  • Patent number: 10761561
    Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Saira Samar Malik, David Joseph Hawkins, Andrew David Tune, Guanghui Geng, Julian Jose Hilgemberg Pontes
  • Patent number: 10725084
    Abstract: A fault diagnosis method for a series hybrid electric vehicle AC/DC (Alternating Current/Direct Current) converter, implementing identifying and diagnosing of an open circuit fault of a power electronic components in an AC/DC converter, and including the following steps: first, establishing a simulation model for a series hybrid electric vehicle AC/DC converter, and selecting a DC bus output current as a fault characteristic; then classifying fault types according to a quantity and locations of faulty power electronic components; next, decomposing the fault characteristic, that is, the DC bus output current by means of fast Fourier transform to different frequency bands, and selecting harmonic ratios of the different frequency bands as fault diagnosing eigenvectors; and finally, identifying the fault types by using a genetic algorithm-based BP (Back Propagation) neural network.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: July 28, 2020
    Assignee: WUHAN UNIVERSITY
    Inventors: Yigang He, Yaru Zhang, Hui Zhang, Kaipei Liu
  • Patent number: 10719904
    Abstract: A parallel processing apparatus includes, a plurality of operational circuits that execute operations for data in parallel, and a control circuit that, upon an end of operations for a first portion of the data, finds estimated operation time for operations for a second portion that is an object of operations subsequent to the first portion, based on target time for operational processing for the data and a data amount of remaining data for which no operation has been executed in the data, finds a second parallelism of the operations for the second portion, based on a first parallelism of the operations for the first portion, a measurement value of operation time for the operations for the first portion, and the estimated operation time, and causes operational circuits, numbering in a number indicated by the second parallelism among the plurality of operational circuits, to execute the operations for the second portion.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Taketoshi Yasumuro, Hirotaka Fukushima
  • Patent number: 10700671
    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 30, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern, Brian S. Leibowitz, Jared Zerbe
  • Patent number: 10678297
    Abstract: A digital state device may include a first circuit terminal that obtains a clock signal from a first integrated circuit. The digital state device may further include a second circuit terminal that transmits the clock signal to a second integrated circuit. The digital state device may further include digital logic circuitry coupled to the first circuit terminal and the second circuit terminal. In response to obtaining an in-band notification signal in reverse of the clock signal and from the second integrated circuit, the digital logic circuitry sets the clock signal to a first predetermined value. In response to the digital logic circuitry determining that the clock signal exceeds a predetermined amount of time at the first predetermined value, the digital logic circuitry sets the clock signal to a second predetermined value that is different from the first predetermined value.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Ciena Corporation
    Inventors: Roger Paul Toutant, Richard Murray Wyatt, Baskaran Soosaithasan
  • Patent number: 10593383
    Abstract: Methods, systems, and devices for system-level timing budget are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10593288
    Abstract: A source driver of a display apparatus includes a receiving controller receiving a first status information signal and outputting a second status information signal and a receiving circuit receiving a transmission signal in response to the second status information signal and recovering the transmission signal to receiving data. The receiving controller includes a transition detection circuit detecting a transition of the first status information signal and outputting a transition detection signal, a delay circuit delaying the transition detection signal by a predetermined time and outputting a delay detection signal, and an output circuit receiving the first status information signal and outputting the second status information signal in response to the delay detection signal.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kihyun Pyun, Sung-jun Kim, Yunmi Kim, Juhyun Kim, Minyoung Park
  • Patent number: 10580465
    Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 3, 2020
    Assignee: Rambus Inc.
    Inventors: Michael L. Takefman, Maher Amer, Claus Reitlingshoefer, Riccardo Badalone
  • Patent number: 10558608
    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 11, 2020
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Patent number: 10554383
    Abstract: An analysis system that is able to obtain correct encryption key is provided. The analysis system includes a processing circuitry configured to function as a cryptanalysis processing unit. The cryptanalysis processing unit includes: a key candidate extraction unit that is configured to extract, from second data, one or more candidates of key data that include an encryption key that enables to decrypt first data encrypted by a specific encryption scheme, based on data indicating a feature of the key data; and a decryption unit that is configured to extract, from the extracted candidates of key data, correct key data that enables to correctly decrypt the encrypted first data, based on a result of decrypting the first data by use of the extracted candidates of key data.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 4, 2020
    Assignee: NEC CORPORATION
    Inventors: Masato Yamane, Yuki Ashino, Masafumi Watanabe
  • Patent number: RE48134
    Abstract: Certain aspects are directed to an interceptor system for characterizing digital data communicated between certain points in a telecommunication system. The interceptor system includes an interface device and a processing device. The interface device can retrieve data from at least one communication link between a radio frequency processing unit and a baseband processing unit of a telecommunication system. The data includes digital data communicated between the radio frequency processing unit and the baseband processing unit. The processing device can determine an interface link protocol for communicating with terminal equipment via the telecommunication system. The interface link protocol can be determined based on an organization of the data retrieved from the communication link.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: July 28, 2020
    Assignee: CommScope Technologies LLC
    Inventors: Thomas B. Gravely, Morgan C. Kurk, Oluwatosin O. Osinusi, Andrew E. Beck, Patrick Boyle