Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

Abstract: A control circuit including a timer circuit and a voltage monitor circuit is provided. The timer circuit enables a trigger signal every a fixed time interval in response to a wake-up event. The voltage monitor circuit is configured to determine whether the operation voltage reaches the expected voltage and includes a signal-generating circuit, a first delay circuit, a second delay circuit, and a determination circuit. The signal-generating circuit generates a reference signal according to the trigger signal. The first delay circuit receives the operation voltage and delays the reference signal to generate a first delay signal. The second delay circuit delays the trigger signal to generate a second delay signal. The determination circuit enables a wake-up signal according to the reference signal, the first delay signal, and the second delay signal in response to the wake-up event.

Abstract: An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.

Abstract: An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction.

Abstract: A method of loading a data string into a Joint Test Action Group (JTAG) shift register is provided. The method includes determining whether the last bit of the data string is equal to one or zero. In response to determining that the last bit is equal to one, the method includes simultaneously setting each flip-flop of the shift register to one, identifying first data string loading bits by removing, from the data string, the last bit and any other bits in a continuous sequence of bits, including the last bit, that are each equal to one, and sequentially loading the identified first data string loading bits into the shift register. A testing apparatus for performing the method and an enhanced JTAG interface are also provided. The method, testing apparatus, and enchanced JTAG interface may reduce the number of clock cycles required to load the shift register.

Abstract: A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

Abstract: Apparatus and methods for controlling a clock signal are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The clock interface circuit includes an oscillator for generating an oscillator signal, and a comparator for controlling operation of the clock interface circuit in a selected clock control mode based on comparing an electrical characteristic of the clock interface pin to a comparison threshold. The selected clock control mode is chosen from a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on a clock interface pin, or a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal.

Abstract: A key-press detection circuit for an information handling system includes a detector circuit, a RC circuit, and a latch circuit. The detector circuit is coupled to a keyboard matrix device, and operates to provides a clock signal in a first state when a particular key of the keyboard matrix device is pressed and to provide the clock signal in a second state when the particular key is not pressed. The RC circuit receives the clock signal and provides a timed clock signal in a third state for a predetermined amount of time in response to receiving the clock signal in the first state. After the predetermined amount of time, the RC circuit provides the timed clock signal in a fourth state. The latch circuit receives the timed clock signal at a clock input, receives a data signal at a data input, and latches an output signal in a same state as the data signal when the timed clock signal changes from the third state to the fourth state.

Abstract: According to one embodiment, there is provided a semiconductor apparatus including a first chip and a second chip. The first chip is electrically connected to a terminal to which a signal from a host device is input. The second chip is electrically connected to the first chip. The second chip has a first duty adjustment circuit. The first chip has a second duty adjustment circuit. The first duty adjustment circuit performs first calibration operation in a first period. The second duty adjustment circuit performs second calibration operation in a second period. The first period and the second period have an overlapping period.

Abstract: An electronic switching device includes a USB interface, a multifunctional module, a microprogrammed control module, a recognition program unit and a transient memory. The USB interface is connected with a computer through a USB cable. The multifunctional module includes a UART circuit unit and a power supply. The UART circuit unit and the power supply are disposed in the electronic switching device. The UART circuit unit is connected between the USB interface and the microprogrammed control module. The recognition program unit is disposed in the microprogrammed control module. The transient memory is disposed in the microprogrammed control module. The microprogrammed control module stores an initial value of the UART circuit unit or a start value of the UART circuit unit in the transient memory to dynamically switch UART function statuses of the UART circuit unit.

Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.

Abstract: Described are methods, systems and computer readable media for data source refreshing using an update propagation graph having a merged join listener.

Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.

Abstract: The present disclosure provides a data synchronization method and apparatus, for synchronizing data between a first system and a second system on a same terminal. Data stored in a storage area corresponding to the first system of the terminal is retrieved; the retrieved data is sent to a remote device to process the data; the processed data is sent back to the terminal and stored in a storage area corresponding to the second system.

Abstract: Problem A sub clock for a sleep mode in a a microcomputer is retained to be operable with high accuracy. Solution A sub clock 20 counts oscillating pulses of a CR oscillating circuit 21 by a loop counter 22, and outputs a clock signal each time the oscillating pulses reach a target count Pm. A CPU 11 counts oscillating pulses of the CR oscillating circuit 21 in a predetermined time measured by a time counter 25 in response to a clock signal of a main clock 13 by a crystal oscillator, and corrects the target count Pm according to a pulse count P thereof. Since the real count state is obtained based upon the clock signal of the main clock having high frequency accuracy without the estimation of the sub clock 20, the high accuracy of the sub clock is retained even if environmental changes such as temperatures occur.

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

Abstract: Aspects disclosed herein relate to activating a single wire protocol (SWP) interface with a circuit card. A single wire protocol (SWP) activation procedure is initiated with a circuit card. During the SWP activation procedure, an unexpected frame may be received, and a different SWP activation procedure may be initiated with the circuit card based at least in part on receiving the unexpected frame during the SWP activation procedure.

Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.

Abstract: The present disclosure enables remote device management. A programmatic interface is associated with each application plug-in. A web server included with the on-device agent provides access to the programmatic interfaces according to open standards such as HTML or XML. The present disclosure enables access to remote devices through existing infrastructure without the need for proprietary systems. An IT administrator or other administrator may remotely access and update software and hardware, track device data plan usage statistics, provide live support, and track current and historical device locations. Further, through the use of the present disclosure developers may provide customizable applications employing plug-ins on the remote device targeted for their own system. This disclosure also enables management of remote devices and the data thereon via a data loss prevention component.

Abstract: A method and apparatus for using multiple data rate (MDR) wiring with encoding is described herein. Single data rate wires are replaced with MDR wires and signals are processed through MDR circuitry. The MDR circuitry may include MDR driver circuitry, MDR repeater circuitry and MDR receiver/decoder circuitry. An encoding circuit may be included in the MDR circuitry to mitigate power consumption due to signal toggling rates. The MDR circuitry may be implemented at multiple clock rates, and with source synchronous bus circuitry and clock gates.

Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.

Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Abstract: Even after power-down, distinction between a transition from a PLL normal-oscillation state and a transition from a PLL self-oscillation is allowed. A semiconductor device includes a first region which, after having transited from a power-supply state to a power-down state, returns to the power-supply state again, a second region which holds a power source voltage regardless of power-down of the first region, and an oscillator which generates a first clock signal supplied to the first region. The first region includes a PLL circuit. The second region includes an information holding unit capable of holding information which can distinguish whether the operation mode of the PLL circuit is a PLL normal-oscillation mode or a PLL self-oscillation mode, and determines the operation mode of the PLL circuit when the first region has returned from the power-down state to the power-supply state, according to the information held in the information holding unit.

Abstract: A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the address-collided slave devices to return their unique identification data. The master device sets addresses of the address-collided slave devices so that each of the slave devices in the communication network has a different address from one another.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.

Abstract: An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry.

Abstract: A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.

Abstract: Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel.

Abstract: A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Abstract: The power saving device and method are provided. The power saving device which applies to a network apparatus includes a Phase-Locked Loop circuit, a computing module and a clock-selecting register, the Phase-Locked Loop circuit is configured to receive a reference clock frequency and generate a clock frequency-increasing signal according to the reference clock frequency; the computing unit is configured to calculate a setting parameter and the clock-selecting register is configured to generate an operating clock signal according to the clock frequency-increasing signal and setting parameter and send the operating clock signal to the network apparatus, wherein the network apparatus adjusts the clock frequency rate according to the operating clock signal.

Abstract: A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to control a supply of clock to the processing unit; and an instruction unit configured to give an instruction for the clock control to the control unit, wherein the control unit controls the gate unit and controls the clock supplied to the processing unit based on an instruction from the instruction unit, whereby securing a higher power saving effect.

Abstract: The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Abstract: Systems and methods for providing resource management in a distributed network are disclosed. A loose collection of devices in a network may not be aware of the power restrictions for other devices. Wall powered devices will generally have drastically different power settings than battery powered mobile devices. The invention provides a federation policy for time that can be used to slave to a local service responsible for understanding the local resource requirements of each device (or node) on the network. In such a distributed time system, all services in a particular time domain may be sped up, slowed down, or completely halted.

Abstract: A timing control circuit includes: a first variable delay circuit configured to receive first data having a first communication speed, and to give a variable delay to the first data; a first multiplexer configured to receive output of the first variable delay circuit, and to convert into second data having a second communication speed different from the first communication speed in accordance with first control signal; a second variable delay circuit configured to receive third data having the first communication speed, and to give a delay corresponding to the delay of the first variable delay circuit to the third data; a decision circuit configured to compare timings of output of the second variable delay circuit and the first control signal; and a control circuit configured to control the delays of the first variable delay circuit and the second variable delay circuit in accordance with output of the decision circuit.

Abstract: Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that all units are connected one after the other in a chain like manner on the busses. The modules cooperate to transition an output signal between different duty cycles and activate and deactivate responsive to timer comparisons.

Abstract: A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

Abstract: An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount.

Abstract: A method of operating a system on chip (SoC), an integrated circuit including the SoC, and a system including the same are provided. The method includes: delaying a data strobe signal; obtaining a setup margin and a hold margin by adjusting a delay of the delayed data strobe signal; and determining a data valid window using the obtained setup margin and the obtained hold margin.

Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.

Abstract: A method for calibrating a memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.

Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

Abstract: A heat dissipation system within a housing of a computer is disclosed. The heat dissipation system includes a heat dissipating fan, a temperature sensor, a rotation speed setting portion, and a performance control portion. The rotation speed setting portion is configured to change a rotation speed of the heat dissipating fan in a stepwise manner based on a threshold temperature and a measurement temperature measured by the temperature sensor. The performance control portion is configured to temporarily reduce the processing capability of a processor within the computer in response to a determination that the measurement temperature has exceeded the threshold temperature during a predetermined period of time.