Abstract: A self-starting transformer-coupled FET multivibrator is constructed to avoid net dc flow in the primary winding of its transformer, driven push-pull by the multivibrator FET's.

Abstract: In an FM receiver including a plurality of cascaded amplifier stages for successively amplifying an IF signal to form a pulse signal which is demodulated to derive an audio signal, an auxiliary amplifier section beside the cascade is provided to amplify a signal developed at an intermediate point in the cascade to form a signal from which a control signal for controlling the gain of an RF amplifier. The auxiliary amplifier section includes a first linear amplifier including degenerative signal feedback followed in cascade by a second linear amplifier including a gain control arrangement. The latter is responsive to a logarithmic gain control signal generated by a logarithmic amplifier in response to the output signal of a peak detector following the auxiliary amplifier. The control signal has a relatively wide control range, e.g., 10 to 500 microvolts of RF input signal, suitable for controlling the gain of an RF stage.

Abstract: A substantially non-loading circuit for measuring voltages in a range with relatively high upper limit uses a resistive voltage divider for scaling down these voltages for application to a digital voltmeter capable of measuring voltages in a range with relatively low upper limit. The loading that the input circuit of the resistive potential divider would place on the circuit being measured is reduced by placing the loading of the potential divider input circuit on an electrically adjustable voltage supply, rather than the circuit being measured. The current loading on the circuit being measured is sensed; and the output voltage of this supply is automatically adjusted by feedback to reduce the sensed circuit. In this way, loading of the circuit being measured is reduced, thus avoiding undesirable reduction of the voltage across the circuit owing to its being loaded.

Abstract: A signal to be quantized is translated to a charge Q and the latter is multiplied by a fraction f to produce a fractional charge packet fQ. Then, another fractional charge packet is produced by multiplying the remainder Q(1-f) of the charge packet by f. This last step is repeated for succeeding remainder charge packets a sufficient number of times until a total of n-1 fractional charge packets have been produced, where n is the number of quantization levels desired. The successive fractional charge packets are compared with threshold levels of different amplitudes to determine the number of incremental charge packets, each of the same size, to be added to one another to form a quantized charge packet.

Abstract: In a television receiver, two tunable traps are incorporated between the RF input and the tuner to attenuate undesired signals symmetrically located in frequency below and above respective desired RF carriers. In one embodiment, the tunable traps are responsive to a tuning voltage for controlling the tuned circuits of the tuner so that the attenuation frequencies of the traps track the frequencies of the RF carriers associated with selected channels. In another embodiment the attenuation frequencies of the traps are moved with respect to the respective frequencies of desired RF carriers to optimize interference reduction.

Abstract: The input offset potential of a transistor amplifier exhibited by a grounded-emitter bipolar transistor or a grounded source enhancement-mode field effect transistor can be too large for certain applications. A preceding differential-input amplifier overcomes this problem.

Abstract: An integrated circuit for processing the IF signal of a radio receiver to produce an audio signal also includes a muting circuit for muting the audio signal, detector circuits for generating a stop signal which, e.g., may be used to stop the operation of a scanning tuner when the IF signal has a predetermined condition, an inhibiting circuit for inhibiting the generation of the stop signal and a signal strength for generating positive-going and negative-going signals representing the amplitudes of an RF input signal.

Abstract: In an integrated circuit structure including IF amplifier stages coupled in cascade by d-c blocking capacitors to restrict the noise bandwidth of an FM receiver in which it is employed and receiving power from a common power supply line, separate operating voltage generating circuits are provided for each amplifier stage to inhibit undesired oscillations. Each voltage generating circuit is decoupled from the power supply line by a respective lateral transistor configuration cooperative with a current mirror amplifier arrangement to supply a reference current to the voltage generating circuit.

Abstract: A digital phase comparator for essentially eliminating the dead zone in the phase correction means of a phase locked loop. The digital phase comparator is arranged to provide respective up and down output pulses to operate respective charge pumps. The up and down output pulses at all times are greater than a predetermined time duration no matter how small the phase difference between comparator input signals. A delay means is provided in the phase comparator logic, which delay means substantially determines such predetermined time duration. The minimum pulse duration of the up and down signals is selected to be at least of a duration sufficient to operate its respective charge pump, thereby overcoming the finite turn on time of the respective charge pump, no matter how small the phase error.

Abstract: The circuitry comprises a source of input signal current, a common-base transistor amplifier or its equivalent supplying a first load means from its output connection, a first resistive means connected at its first end to the source of input signal current and at its second end to the input connection of the common-base transistor amplifier or its equivalent, a voltage follower with input connection from the first end of the first resistive means, a current mirror amplifier supplying a second load means from its output connection, and a second resistive means connected at its first end to the output connection of said voltage follower and connected at its second end to the input connection of the current mirror amplifier.

Abstract: A logic level converter for translating an input signal that swings between first and second voltage levels to an output signal that swings between third and fourth voltage levels. The input signal and its complement are first translated to the desired output levels in a pair of conventional CMOS inverters to produce complementary logic signals. The faster edge of each translated logic signal is used by logic means to control the output signal. Specifically, the leading edge of one logic signal and the trailing edge of the other logic signal are used to control the output signal. The resulting logic level shift circuit provides both fast rise and fall times, and substantially equal propagation delays for both high-to-low and low-to-high signal transitions.

Abstract: An integrated circuit having circuitry for clamping input terminals that remain unconnected after assembly into a system. A transistor is connected to clamp the input terminal to reference potential and provide regenerative feedback to a NAND circuit forming a latch which maintains the transistor on when the input terminal would otherwise be left floating. Alternatively, when the terminal is connected to supply potential, the transistor is maintained "off", precluding loss of power.

Abstract: Within a single pack tape cartridge, a bearing szrface is integrated on the cartridge case to preclude segments of the tape pack from telescoping into clearance space and thereby a retaining ring is eliminated from the tape cartridge assembly.

Abstract: A complementary field-effect transistor (FET) amplifier with means for controlling peak cross-over current. A substantially constant current is established in the drain-source conduction paths of a pair of reference transistors by degenerative feedback from the conduction paths to the respective gate electrodes thereof; wherein the reference transistors have similar characteristics to the respective amplifier transistors. The resulting sum of the gate-to-source voltages of the reference transistors is used to apply a bias voltage between the gate electrodes of the transistors in the FET amplifier so that the sum of the gate-to-source voltages of the amplifier transistors is equal to the sum of the respective gate-to-source voltages of the reference transistors during the cross-over current condition. Cross-over current is thereby limited to a predetermined value proportional to the substantially constant current established through the reference transistors.

Abstract: A temperature-sensitive voltage divider for monolithic i.c.'s using singly and doubly diffused resistors avoids the problems with tracking their resistance characteristics owing to diffusion process variations. This is done by using the pinch resistor in conjunction with the base-emitter circuit of a bipolar transistor arranged in common-collector amplifier configuration. The impedance transformation properties of the transistor ease the problems of scaling otherwise encountered in many potential divider arrangements of supply and doubly diffused resistors. The utility of the voltage divider is illustrated in the shunt regulation of the operating voltage of an AM radio receiver.

Abstract: First and second direct-coupled cascade connections of like numbers of transistors of the same conductivity type are connected in push-pull. The output stages have common-emitter and common-collector-amplifier transistors, respectively, while earlier stages have common-collector and common-emitter-amplifier transistors, respectively, the common-emitter-amplifier transistor working into a constant current generator collector load.

Abstract: In this relaxation oscillator first and second electrically controlled constant current generators are used to provide proportionately related first and second currents to first and second terminals, respectively, between which the timing capacitor is connected. Set-reset, or R-S, flip-flop means is set and reset by the voltage at the first and second terminals, respectively, departing in a first sense from the voltage at a reference voltage bus by a predetermined amount. First switching means responds to the R-S flip-flop reset condition to complete a connection of the first terminal to the reference voltage bus and responds to the R-S flip-flop set condition to interrupt that connection. Second switching means responds to the R-S flip-flop set condition to complete a connection of the second terminal to the reference voltage bus and responds to the R-S flip-flop reset condition to interrupt that connection.

Abstract: A signal to be quantized is translated to a charge Q and the latter is multiplied by a fraction f to produce a fractional charge packet fQ. Then, another fractional charge packet is produced by multiplying the remainder Q(1-f) of the charge packet by f. This last step is repeated for succeeding remainder charge packets a sufficient number of times until a total of n-1 fractional charge packets have been produced, where n is the number of quantization levels desired. The successive fractional charge packets are compared with threshold levels of different amplitudes to determine the number of incremental charge packets, each of the same size, to be added to one another to form a quantized charge packet.

Abstract: A complementary symmetry inverter comprising two field effect transistors and a current mirror amplifier. A constant bias current is supplied to the master path of the current mirror amplifier. The slave path of the current mirror amplifier and one of said field effect transistors are connected to form a switched current source in series with the other of said transistors. The switched current source limits the peak value of the switching current pulse in the inverter in fixed relation to the current in the master path of the current mirror amplifier when the inverter switches between logic states. The switched current source also limits the current between the inverter output and an external device.

Abstract: A dynamic current supply is connected between the emitter electrode of an output transistor and a point of reference potential, to progressively increase the magnitude of the flow of current therebetween, as the output signal at the emitter electrode approaches the point of reference potential. The dynamic current supply includes a current mirror, the output of which is in the path of and controls the flow of current. An MOS transistor, the conductivity of which is a function of the difference in potential between the operating voltage supplied to the output transistor and the output signal, supplies the input or control current to the current mirror.