Abstract: A receiver which may be tuned in a step, slow, or fast tuning mode through operator actuation of up and down tuning switches is disclosed. The counting direction of an up/down counter as well as its counting mode is determined by which of the status of the two switches. Control circuitry responds to the status of the switches to discretely increment or decrement the counter in response to momentary actuation of a switch. The counter is clocked at a slow rate if a switch is continuously actuated for a predetermined time interval and at a high rate if both switches are actuated concurrently.
Abstract: Steering logic interconnects the individual portions of a partitioned counter and are controlled by test logic to selectively apply a clock input to the first stage of each portion of the counter in sequence and to detect overflow of the individual portions so as to determine whether the various stages of each portion are properly connected together, as well as to determine whether the steering logic properly interconnects the various portions of the counter.
Abstract: Digital frequency measuring circuitry is disclosed which includes a first shift register, the content of which is increased by a fixed amount at the beginning of each cycle of the input signal to be measured. Thereafter the content of the first register is caused to exponentially decay until the next input cycle is detected where the process is repeated. At the beginning of each cycle of the input signal, the content of the first register is transferred to a second or memory register where the data is used to drive a gage or other output device. To improve gage performance during low frequency input the memory register is also updated whenever the content of the first register is less than the content of the memory register. Also, if the input signal is removed any significant residual in the first register is eliminated by decrementing the first register to insure that the gage accurately represents the input condition.
Abstract: A multiple input window detector is disclosed which includes a balance pair of common base PNP transistors having multiple emitters connected to respective inputs for comparing either input to an upper threshold level established by a voltage divider. A pair of common emitter PNP transistors compare the inputs to a lower threshold level. The two outputs of each comparator are interconnected and the combined currents control an output stage which is driven to one state when both inputs are within the window established by the divider and is driven in the other state if either input is outside the window.
Abstract: Disclosed is a method and apparatus for automatic measurement of strain in a formed sheet metal sample. Prior to the forming operation, a grid of circles is imprinted on the sample and during the forming operation the circles are stretched to ellipses. The formed sample is exposed to an instrumentation camera and a digitized image of the pattern on the sample is stored in a digital computer. The computer is programmed to segment the image to distinguish the elliptical patterns from the background; to extract boundary points on an elliptical pattern and fit these points to an ellipse. Strain is determined as a function of the diameters of the fitted ellipse as well as the chord lengths of the actual pattern along the axes of the fitted ellipse.
Abstract: A plurality of permanent magnet DC motors are grouped into two banks. One side of each motor in one bank is connected to a first common supply conductor while one side of each motor in the other bank is connected to a second common supply conductor. Independently operable switches are provided for connecting the other sides of respective ones of the motors in the first and second banks to a third common supply conductor. Three additional power switches are provided for reversibly connecting a source of potential across either bank of motors. By proper switch selection one or more motors in either of the banks may be operated in a selected direction of rotation.
March 31, 1980
Date of Patent:
September 8, 1981
General Motors Corporation
Alfonso Vazquez-Cuervo, Frederick T. Richards, Daniel V. Bafunno, George Papacostas
Abstract: A noise tolerant time division multiplex system including a transmitter and receiver, each constructed as a monolithic integrated circuit and interconnected by a serial data wire. Data as well as power is supplied to the transmitter from a plurality of parallel connected input switches. The transmitter includes a parallel in/serial out shift register controlled by timing logic and further includes a tri-state driver for generating a three-level serial output signal indicative of the status of the input switches. The data is generated at a high rate to eliminate any deleterious effects of noise on the system. The receiver chip receives a regulated energizing potential from the transmitter chip over two additional wires, generates a timing signal from the three-level signal and loads the data in binary format into a serial in/parallel out shift register.
July 2, 1979
Date of Patent:
June 30, 1981
General Motors Corporation
James W. McNamee, Gerald E. Homstad, Alfonso Vazquez-Cuervo, Kenneth J. Henry
Abstract: A portable calculator which includes circuitry for disabling operation of the display until a predetermined sequence of digits are entered from the keyboard. The circuitry includes a plurality of latches which are set in sequence in response to application of power to the calculator. The setting of the final latch disables the display so that although the computer chip is operative and responds to entries from the keyboard, no digits are displayed. Decoder circuitry responsive to the segment outputs of the computer chip permits the plurality of latches to be sequentially reset from the computer chip when the predetermined sequence of digits are entered from the keyboard or the computer chip is commanded to perform a mathematical calculation the result of which corresponds to the predetermined sequence of digits.
Abstract: A circuit for terminating the signal seeking mode of operation of an AM receiver includes a comparator which responds to a composite signal comprising a broadband IF signal and the detected IF signal strength. A control signal is produced when the composite signal exceeds a predetermined threshold. The broadband component of the composite signal is effective as a blanking potential when the receiver is off-channel. A second comparator is utilized to establish local sensitivity so that local and distant sensitivity settings are not interrelated.
August 8, 1979
Date of Patent:
April 14, 1981
General Motors Corporation
Eldred H. Wiechmann, Richard A. Kennedy, Myron G. Padgett
Abstract: An accelerometer utilizes a pair of SC-cut crystals which respond differentially to acceleration inputs. Each crystal exhibits a highly temperature sensitive resonant mode and a relatively temperature insensitive resonant mode. Both modes are excited simultaneously by an oscillator. The difference frequency data between respective modes of each crystal, as well as the difference frequency data between the two modes of one of the crystals, is processed to obtain a temperature compensated value of acceleration.
Abstract: A microprocessor based engine control system including an engine control unit for producing a plurality of pulse width modulated output signals of programmable frequency. The pulse width and frequency of each output is contained in a control word provided to the engine control unit. The control word contains a pulse width number and a frequency code. The control unit includes a free-running counter and logic means which switches the output signal to one level when the number of stages of the counter defined by the frequency code are all zero and switches the output signal to a second level when the content of the aforementioned number of counter stages is greater than the pulse width modulated number.
Abstract: An engine control system includes a microprocessor responsive to engine operating parameters for developing control words representing a desired dwell and firing time for use in controlling engine spark timing. An engine control unit is coupled to the microprocessor and utilizes the control words in calculating the desired rise and fall of the spark timing output relative to reference pulses, indicative to engine crankshaft position. The engine control unit includes a free-running counter which serves as a time reference for determining the period of the input reference pulses and for predicting the time of rise and fall of the output. Prediction of the next rise is made when the output falls and prediction of next fall is made when the output rises. Predictions are made on the assumption of constant frequency reference pulses. Errors resulting from this assumption are corrected when a reference pulse occurs.
Abstract: A time division multiplex system includes pulse width modulation to provide an automobile interrogate and control system whereby either the driver or front seat passenger can manually-operate switches mounted on doors to control door locks, windows and seat positioners. The system includes a transmitter module located in the left front door which transmits information to receiver modules interconnected by a data line and located in the passenger doors and under the front seat. The receiver in the right front door is capable of modifying the information received from the transmitter and placing the modified data on the data line to permit control of the right seat adjuster and all of the vehicle doors from the control located in the right front door. Stall of window motors or door lock solenoids is avoided through priority logic.
Abstract: A control and indicating circuit for an inflatable safety system in which oppositely poled diodes provide isolated firing and monitoring networks interconnected between single pole, double throw impact switches. In one embodiment the diode in the firing network is light activated.
Abstract: A vibratory gyro including a hemispherical high Q resonator supported by an inner housing carrying a circular forcer electrode and sixteen discrete forcer electrodes. The orientation of the vibrating pattern in the resonator is electrostatically sensed by eight pickoff electrodes located on the inner spherical surface of an outer housing which establish two pickoff axes separated by 45.degree.. Signals obtained from the pickoff electrodes are utilized to develop a drive signal to the circular forcer electrode to electrostatically maintain a predetermined amplitude of pattern vibration and to develop drive signals for appropriate groups of discrete forcer electrodes to eliminate any phase error between components of the pattern along the two pickoff axes.
Abstract: A resistor coded anti-theft system particularly adapted for incorporation as original equipment on a motor vehicle is disclosed. The ignition system is defeated unless an ignition key having both the proper mechanical code and proper code resistor is used to start the vehicle. A selectively destructible fuse device is incorporated in the circuitry to permit determination of the value of the proper code resistor during a final stage of vehicle assembly.
Abstract: A system for determining the value of an angle represented by first and second analog signals having amplitudes which are a function of the SIN and COS of the angle. The SIN and COS signals are full wave demodulated in such a manner that the demodulated signals are always of opposite polarity and the smaller of the two signals is continuously integrated in an integrator while the larger of the two signals is sample data integrated in the integrator to maintain the output of the integrator within predefined upper and lower limits. Angle computation is then performed as a function of the ratio of the number of complete half cycles of the demodulated signals during a fixed time interval plus the change in the output of the integrator since the previous time interval.
Abstract: A digital key system is disclosed which includes a programmable read only memory which is automatically programmed with the code for unlocking the system during initial removal of the key from the lock.
Abstract: A digital speed control system including a processor performing arithmetical and logic operations in response to command inputs from the operator to maintain the present vehicle speed, to accelerate at a substantially constant rate to a new cruising speed or to a previously established cruising speed is disclosed. Certain processor operations are phased to speed sensor pulses to permit rate of change of speed computations to be performed with minimum hardware.
Abstract: A vehicle security system includes a door locking mechanism and control circuitry which prevents access to the vehicle interior unless a door lock key is used thus making it unnecessary to specifically lock the doors upon exiting the vehicle. Steering shaft lock means are also energizable by operation of the door lock key permitting elimination of the ignition key and lock cylinder.