Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.

Abstract: A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.

Abstract: A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107).

Abstract: A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer which does not overlie the alignment mark. The removal exposes a portion of the alignment mark protection layer which does not overlie the alignment mark and the exposed portion of the alignment mark protection layer is then removed. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion thereof using an edge-bead removal tool, thereby allowing for the formation of an alignment mark protection structure without an extra masking step.

Abstract: A dataform reader which includes a hand-portable sized housing and an image assembly included within the housing. The image assembly includes a lens array or other optical system for obtaining a plurality of images of the dataform when positioned a given distance from the dataform. Each of the plurality of images is obtained relative to a different respective best focus length from the image assembly. The dataform reader further includes processing circuitry within the housing for selecting, from among the plurality of images, an image satisfying a predefined focus criteria. The selected image may then be decoded.

Abstract: A method for fabricating a memory device is provided. A first polysilicon (poly I) layer is formed over a substrate. Poly I isolation rows are etched into the poly I layer so as to form electrically isolated poly I lines. An oxide-nitride-oxide (ONO) layer is formed over the poly I lines and field oxide portions exposed via the poly I isolation rows. A second polysilicon (poly II) layer is formed over the ONO layer. Poly II isolation rows are etched into the poly II layer so as to form electrically isolated poly II lines, the poly II isolation rows being perpendicular in direction to the poly I isolation rows, the poly II isolation rows exposing portions of the ONO layer. Heavy ions are implanted into portions of the poly I layer via the exposed portions of the ONO layer, wherein the heavy ions disrupt silicon bonds of the poly I layer portions. The exposed portions of the ONO layer and the poly I layer portions are substantially etched away.

Abstract: A method (100) of forming a reflective reticle blank includes forming (106) a reflective layer (108) over a flat substrate (104) and coupling a low thermal expansion material (112) to the reflective layer (108). After coupling the low thermal expansion material (112) to the reflective layer (108), the flat substrate (104) is removed. By forming the reflective layer (108) on the flat substrate (104), a low-defect, high reflectivity reflective layer (108) is formed. In addition, by removing the flat substrate (104), the reticle blank uses the low thermal expansion material (112) as substrate and exhibits minimized distortion during processing due to its low thermal expansion material.

Abstract: A method of preventing poly stringers in the formation of a memory device includes the steps of forming at least one field oxide region in a substrate and forming a tunnel oxide over the substrate. A first polysilicon layer is then formed over the tunnel oxide and a poly mask having a mask profile is formed over the first polysilicon layer. The first polysilicon layer is then etched in portions exposed by the poly mask, thereby creating a first polysilicon layer etch profile, wherein the first polysilicon layer etch profile is substantially ideally anisotropic and independent of the mask profile. An insulating layer and a conductive layer is then formed over the etched first polysilicon layer and portions of the conductive layer are then etched to form word lines. The insulating layer is then etched in regions adjacent the word lines, thereby leaving a substantially vertical insulative fence along the first polysilicon layer etch profile.

Abstract: A single button contrast control which can bi-directionally adjust a contrast function in one of two directions so as to increase or decrease the contrast of a display. An interrupt generator generates an interrupt for each user activation of a single button control key. A control circuit incrementally adjusts the contrast function in accordance with the interrupts generated. If no interrupts are generated within a predetermined period of time following a previous interrupt, the control circuit changes the direction in which the contrast is incrementally adjusted so that the next time a user activates the single button control key the control will be adjusted in the other direction.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.

Abstract: A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner which provides for improved writeability of OPC independent of process push or bias. Alternatively, the data storage medium contains mask layout data which includes a second mask data portion. The second mask data portion corresponds to a feature having an exterior corner and includes a multi-level or stepped outer serif on the exterior corner. The stepped outer serif also provides for improved writeability of OPC independent of process push or bias.

Abstract: A method (100) of providing critical dimension uniformity in a radiation sensitive film (104) includes the steps of forming (102) the radiation sensitive film (104) over a substrate (106) and exposing (110) the radiation sensitive film (104) to radiation (56) using a mask (50) having a pattern thereon, wherein a first feature (52) and a second feature (54) on the mask (50) are intended to provide the same critical dimension on the radiation sensitive film (104). The exposure step (110) creates a non-uniform exposure pattern (60) on the radiation sensitive film (104) corresponding to the mask pattern due to various anomalies in the exposure process or in the mask itself. A transferred first feature (84) critical dimension on the radiation sensitive film (104) which corresponds to the first mask feature (52) is larger than the second transferred feature (86) critical dimension which corresponds to the second mask feature (54) due to the radiation non-uniformities or imaging non-uniformities.

Abstract: A mask (50) for use in lithographic printing includes a pattern (54) formed of a material which is substantially opaque with respect to a wavelength of radiation being used in the lithographic printing. The pattern (54) on the mask (50) corresponds to a desired feature to be formed on a substrate and includes a grating (58) having an alternating pattern of opaque and transparent regions (60, 62). The alternating pattern provides destructive interference of radiation at the substrate in a region corresponding to the desired feature due to diffraction, thereby improving resolution at the substrate. In addition, the alternating pattern (60, 62) on the mask (50) increases a number of focal planes at which the destructive interference occurs and thereby improves a focus process latitude by providing an acceptable resolution over variations in a distance between the mask (50) and the substrate.

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor metal oxide.

Abstract: A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the material. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the material. The measuring system provides material temperature related data to a processor which determines the temperature of the respective portions of the material. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the material and provides for the heating thereof.

Abstract: A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.

Abstract: A method of forming a NAND-type flash memory device (200) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.

Abstract: A system for detecting defects in an interlayer dielectric (ILD) interposed between two conductive lines is provided. The system includes a processor for controlling general operations of the system. The system also includes a voltage source adapted to apply a bias voltage between the two conductive lines and induce a leakage current across the ILD. The system employs a light source to illuminate at least a portion of the ILD and enhance the leakage current. A current source is used to measure the induced leakage current, the current source being operatively coupled to the processor. The processor determines the existence of a defect in the ILD based on the measured leakage current.

Abstract: A reworkable EUV mask (100) includes a substrate (40), a reflective layer (42) overlying the substrate (40), and a buffer layer (44) overlying the reflective layer (42). An absorbing layer (102) composed of primarily a non-heavy metal material overlies the buffer layer (44) for absorbing radiation which is incident thereon. The absorbing layer (102) exhibits a substantially high etch selectivity with respect to the reflective layer (42) and thus is easily removed without substantially impacting the reflectivity of the reflective layer (42) during rework.