Abstract: A data processor includes 32 user registers arranged in two banks of 16 registers each. 4-bit addressing is provided. A 16-bit map register determines the bank from which an addressed register is selected. This determination is made individually for each address. The map register is readable and writable so that the mapping of addresses to banks is under program control. This arrangement provides for accessing a large number of registers using a short address code; registers remaining addressable after a remapping retain their addresses.

Abstract: An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.