Abstract: A method of determining a holdup value for a multiphase fluid. A first holdup component is calculated using a first detection technique which is insensitive to small inclusions of a first fluid constituent (hydrocarbons) dispersed in a second fluid constituent (water). A second holdup component is also calculated using a second detection technique which determines a percentage of the small inclusions of the first fluid constituent that are dispersed in the second fluid constituent. The first and second holdup components are then combined to yield a total holdup value. The method can further compensate for displacement of the second fluid constituent by the small inclusions of the first fluid constituent. The second holdup component is preferably calculated by inferring a maximum heavy phase density (MHPD) of the multiphase fluid.

Abstract: A floor anchor and leveler system for an electronic equipment rack has a leveler shaft welded or otherwise rigidly attached at the upper end to a perpendicular base plate. A leveler foot and jam nut threads onto the leveler shaft. A threaded bolt extends coaxially through the leveler shaft and engages a floor plate which is rigidly attached to the floor using anchor bolts or other means. The jam nut and leveler foot are loosely threaded onto the leveler shaft, sufficiently high to allow the caster to contact and roll on the floor. The rack is positioned on its casters until each of the floor anchor and leveler systems, which are each attached to an underside of the rack, is located and centered above its corresponding threaded floor plate anchor hole. After positioning the rack, a tie-down bolt is installed coaxially through each leveler shaft and loosely engages the threaded floor plate and anchor hole.

Abstract: A method and system in a computer network for dynamically bundling and launching hypertext files within archive files, wherein the computer network includes at least one client connectable to one or more servers. Initially, an archive file is established within the computer network wherein particular subroutines are maintained. Thereafter, a particular hypertext file is associated with a selected subroutine maintained within the archive file. The particular hypertext file and the selected subroutine are subsequently bundled together within the archive file. Thereafter, the archive file is automatically transmitted to the client from a server maintained within the computer network, in response to a client request to download the hypertext file, such that the subroutine and the hypertext file are downloaded within a single selected archive file from the server, thereby reducing download time and increasing data packaging efficiency.

Abstract: A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock).

Abstract: The low profile antenna assembly comprises a generally rectangular frame member housing a planar antenna. A radar absorbing material is attached to the front side of the housing with a radome covering the front side of the planar antenna and attached to the frame member. The planar antenna is a microstrip array fed by a beam forming network that uses either delay lines or phase shifters to electronically steer the antenna pattern horizontally and vertically. The antenna assembly is weatherproofed, painted and flush mounted against a building surface for camouflaging the antenna assembly from observers at a distance.

Abstract: A switch that has a plurality of inputs in which cells are received at these inputs. Each cell received at the inputs of the switch contain routing information. A routing means is employed to route the cells received at the inputs of the switch to outputs using routing information in which a number of the cells are misrouted by the routing means during the process of routing the cells to the outputs. Bus means is employed to route a cell to the destination in which the bus means is connected to the routing means. The bus means routes misrouted cells that are misrouted from the destination by some selected amount.

Abstract: An apparatus for improving I/O pin interfaces for serial data communications is disclosed. In accordance with a preferred embodiment of the present invention, an improved serial interface is provided, which comprises an oscillator input, a signal input, a counter, a register, and a data output. The counter is utilized to count the number of cycles of the oscillator input for which the signal input is asserted. The register is utilized to receive a value from the counter when the signal input is next de-asserted. The data output is at a first logical state when the signal input is asserted for fewer oscillation cycles than the value stored in the register and the data output is at a second logical state otherwise, such that only one I/O pin is required for serial communications.

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. Program instructions in the processor select a second associativity level of a known appropriate level, and implement the second associativity level in the cache using a second mapping function. Application software may provide the program instructions, wherein the application software has procedures that may result in cache "strides" at particular associativity levels, and the known appropriate level is chosen to lessen memory latencies due to strides. Alternatively, the program instructions may be part of an operating system which monitors memory address requests, determines how efficient a procedure will operate at different associativity levels, and selects a most efficient level for the known appropriate level.

Abstract: To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied.

Abstract: A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.

Abstract: A hard disk drive connector with elastomeric shock mounts reduces the amount of mechanical vibration or shock which can travel to or from the head disk drive. The shock mounts are placed between the system components and the mechanical fasteners of the connector to mechanically isolate the connector. The shock mounts attach to the head disk assembly where they work through compression beams to the card electronics. This configuration isolates the head disk assembly from shock coming from the system through the card electronics. It also isolates vibration emitted from the head disk assembly to the system.

Abstract: A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received at the cache. In response to receipt of the first cache operation request, which specifies a particular entry among the plurality of entries, a single access of a coherency state associated with the particular entry is performed. Thereafter, in response to receipt of the second cache operation request, a determination is made whether servicing the second cache operation request requires replacement of one of the plurality of entries. In response to a determination that servicing of the second cache operation request requires replacement of one of the plurality of entries, an entry is identified for replacement. If the identified entry is the same as the particular entry specified by the first cache operation request, the identified entry is replaced only after servicing the first operation request.

Abstract: A method and system are provided within a communication system to quickly make a connection with an access point by using a simple operation. When a communication terminal, such as a personal computer (PC) that has a communication function, is to access a communication network, one of the access points that is the most accessible is selected based on access experience data acquired from past access processing, and the connection at the access point is performed.

Abstract: A multiprocessor data processing system includes a shared main memory and a plurality of processors connected to the memory utilizing a system bus. Data is transferred utilizing the system bus. The plurality of processors include a first processor and a second processor. The first processor includes a first cache, and the second processor includes a second cache. The multiprocessor data processing system executes a test program. During execution of the test program, a first and a second trace are generated. The first trace is generated by monitoring all events occurring at a first location within the system. The second trace is generated by monitoring all events occurring at a second location within the system. Each event is associated with a time of occurrence of that event. The first trace includes each event which was monitored at the first location and the time associated with each event.

Abstract: A method of maintaining cache coherency in a multi-processor computer system, which avoids unnecessary writing of values to lower level caches in response to write-through store operations. When a write-through store operation is executed by a processing unit, the modified value is stored in its first level (L1) cache, without storing the value in a second level (L2) cache (or other lower level caches), and a new coherency state is assigned to the lower level cache to indicate that the value is held in a shared state in the first level cache but is undefined in the lower level cache. When the value is written to system memory from a store queue, the lower level cache switches to the new coherency state upon snooping the broadcast from the store queue. This approach has the added benefit of avoiding the prior art read-modify-write process that is used to update the lower level cache.

Abstract: A method for rebuilding contents of a malfunctioned direct access storage device within a log-structured array is disclosed. In accordance with the method and system of the present invention, each direct access storage device within a log-structured array is divided into multiple segment-columns, and each corresponding segment-column from each direct access storage device within the log-structured array forms a segment. A segment is first located within the direct access storage devices. A determination is made as to whether or not the segment is empty. In response to a determination that the segment is empty, a pointer is moved within a segment-column mapping table from pointing to a segment-column in the malfunctioned direct access storage device to point to a segment-column in a spare direct access storage device of the segment.

Abstract: A case-based reasoning system is disclosed that includes a case database and a search engine. The case database is capable of storing a plurality of cases that each include one or more attributes that each have an associated match weight. Match weights of attributes in different cases are separately specified. In response to receipt of an incident including one or more input terms, the search engine scores the relative closeness of a selected case to the incident utilizing the match weights of attributes in the selected case that match input terms in the incident.

Abstract: The invention provides a system and method of enhancing efficiency in a data processing system having a processor, a memory, and a multitasking operating system for managing the processor and the memory. A normal and an expedited scheduling path are provided for scheduling tasks on the processor. The tasks are each assigned a priority for execution on the processor. A queue is provided for the placement of tasks ready for execution. Upon entry into the ready-to-run queue, the execution priority of the new task is compared to the execution priority of the executing task. Responsive to the new task holding a higher execution priority or to absence of an executing task, the expedited scheduling path is invoked. Otherwise the normal scheduling path is invoked.

Abstract: One aspect of the invention relates to a method for synchronizing control signals with scaled digital video data.

Abstract: A method and system for introducing flux onto at least one surface of a solder pump achieve their objects as follows. A solder pump nozzle is submerged into a flux reservoir. In response to such submersion, the flux in the reservoir is actively introduced into the solder pump nozzle. In one embodiment, the active introduction is achieved by creating a negative pressure in a solder pump nozzle such that flux fills a vacated volume. The created negative pressure is produced by moving a solder column, contained within the solder pump nozzle, under the influence of an applied electric current and an applied magnetic field.