Abstract: Power measuring receiver (PMR) methods and apparatus for measuring power of signals are provided in which a high frequency measuring circuit (HFMC), a conversion measuring circuit (CMC), and an intermediate frequency measuring circuit (IFMC) work in conjunction with each other to measure a wide power range of signals. The HFMC may measure relatively high power signals at high frequency. The CMC may convert the high frequency signal into an intermediate frequency signal so that both the CMC and the IFMC can accurately measure low power signals. The CMC may also set the minimum noise bandwidth associated with gain stages in the IFMC. The intermediate frequency may provide the IFMC with the ability to perform low power measurements at a reduced DC power consumption.

Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

Abstract: A method and system for scanning bar code data that can be published in near real time on Internet or intranet sites. The format is preferably XML-based, so the data is ready for e-commerce applications without further manipulation or conversion. The data can also be translated to more traditional bar code formats for backward compatibility with established barcode scanning practices.

Abstract: Systems and methods of modeling a best-guess semiconductor process flow for fabricating a desired semiconductor device are provided. The best-guess process flow is modeled using an inverse modeling technique. This technique reverse engineers a desired semiconductor device to synthesize a model of a fabrication process that is likely to produce the desired semiconductor device. First, a desired device having one or more desired characteristics is modeled. Then, various process and material parameters, constraints, and actual measured data are used to synthesize one or more unique software models that represent a process flow likely to fabricate the desired device. If more than one process flow is modeled, various parameters are modified iteratively until a unique process flow model is synthesized.

Abstract: An interactive system is provided in which information is displayed in response to the entry of the digits of a channel number. The interactive system may be implemented on a television, a computer, or a radio system. The displayed information may be program listings information such as the channel designator or the program currently airing on the channel. The displayed information may also be a list of channels. The list of channels may be associated with the entered digits, may be component channels, or channels of the same type and may be sorted by various techniques such as numerically, by favorite channels, by type, etc. The interactive system may allow a user to specify a source identifier to channels from different sources and display the channels with the source identifier when they are entered.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract: An interactive wagering system is provided in which users may download electronic racing forms to electronic books. The content of the racing form may be directed toward horse racing. The racing form may be interactive. When a user selects an item from a racing form displayed on the electronic book, the user may be presented with additional information or interactive screens that provide racing-related services such as interactive wagering opportunities. The electronic book may be provided with updated racing data. The user may adjust delivery settings for the racing data. News flashes and other real-time reports may be provided to the electronic book. Such reports may be based on the user's preferences and the user's monitored interests. The electronic racing form may include racing data, racing articles, and advertisements.

Abstract: A leadframe is disclosed. The leadframe comprises a frame characterized by a substantially rectangular outline, a die paddle with a receiving surface, and a plurality of support members that connect the frame to the die paddle. The leadframe further comprises a plurality of leads connected to the frame, that will eventually serve to electrically connect an integrated circuit mounted on the die paddle to an external electrical device. The die paddle lies in a lower horizontal plane. A plurality of support members connect the frame with the die paddle. As projected on to a vertical plane that is perpendicular to the side of the frame to which a support member is attached, the offset angle between the support member and a vertical axis is less than 45 degrees.

Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

Abstract: The motor-generator circuitry of a flywheel energy conversion device can be utilized to preheat the rotor of the flywheel device. It may be desirable to preheat the rotor prior to normal operation because a rotor operating in cold temperature may be more susceptible to brittle fracture or other damage than a rotor operating at a specified operating temperature. The present invention may utilize the principle of induction heating to preheat the rotor. In preferred embodiments, high frequency current may be passed through armature windings of the motor-generating circuitry to induce surface currents into the periphery of the rotor. Heat may then be generated in portions of the rotor receiving the induced currents and then radiate from those portions to raise the rotor temperature to a desired level.

Abstract: The present invention relates to analog computation circuits that use a synchronous demodulator topology which can be configured to perform arithmetic computation, power measurements, and/or energy measurement of various analog signals. The computation circuits have circuitry that generates an output signal based on the values of a first input signal, a second input signal, and a reference signal. This invention provides accurate computation of two signals by using modulation circuitry (e.g., &Dgr;-&Sgr; modulation circuitry), demodulation circuitry (e.g., multiplying digital-to-analog converters), delay circuitry, and output circuitry.

Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

Abstract: Power measuring receiver (PMR) methods and apparatus for measuring power of signals are provided in which a high frequency measuring circuit (HFMC), a conversion measuring circuit (CMC), and an intermediate frequency measuring circuit (IFMC) work in conjunction with each other to measure a wide power range of signals. The HFMC may measure relatively high power signals at high frequency. The CMC may convert the high frequency signal into an intermediate frequency signal so that both the CMC and the IFMC can accurately measure low power signals. The CMC may also set the minimum noise bandwidth associated with gain stages in the IFMC. The intermediate frequency may provide the IFMC with the ability to perform low power measurements at a reduced DC power consumption.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

Abstract: The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A convertible article of furniture that is converted between a first position, in which the article preferably provides a relatively low, flexible, flat surface, where the article can act as a bed, and a second position, in which the article acts preferably provides a relatively high, rigid, flat surface is provided, where the article can act as a table. The transition between bed and table, and back again, is provided by changing the position of engagement of the support of the surface structure as provided by a base member with respect to the surface member. In the first position, the base member provides support distant from a central longitudinal axis of the surface, substantially about the sides of the surface, thereby allowing the surface member to be flexible along and about its central longitudinal axis and the surface is supported in a lower position.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.