Patents Represented by Attorney, Agent or Law Firm Arnall Golden & Gregory, LLP
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Patent number: 6830514Abstract: A system and method of playing a lottery-type game are provided. The game comprises obtaining at least one player-selected combination, or concatenated indicia string, such as from a series of one or more columns on a game play slip. A first random combination, or concatenated indicia string, is generated by a gaming administrator and it is determined whether at least one of the player-selected combinations matches the gaming administrator generated combination. Regardless of whether any player-selected combinations match the first gaming administrator generated combination, at least a second gaming administrator generated combination, or more, may be provided for a player to determine whether at least one of the player-selected combinations matches the second gaming administrator generated combination. A payout amount may be awarded based upon the number of player-selected combinations and gaming administrator generated combinations matched.Type: GrantFiled: December 13, 2001Date of Patent: December 14, 2004Assignee: Scientific Games Royalty CorporationInventors: Mark G. Meyer, Joseph J. Tracy, Fred L. Richard, Deborah Jonasson, Keith A. Jonasson
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Patent number: 6823430Abstract: A memory system for a computational circuit having a pipeline includes at least one functional unit and an address generator that generates a memory address. A coherent cache memory is responsive to the address generator and is addressed by the memory address. The cache memory is capable of generating a cache memory output. A non-coherent directory-less associative memory is responsive to the address generator and is addressable by the memory address. The associative memory receives input data from the cache memory. The associative memory is capable of generating an associative memory output that is delivered to the functional unit. A comparison circuit compares the associative memory output to the cache memory output and asserts a miscompare signal when the associative memory output is not equal to the cache memory output.Type: GrantFiled: October 10, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventor: David A. Luick
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Patent number: 6819469Abstract: A high-resolution spatial light modulator and systems incorporating the modulator. The modulator includes an array of optically multistable reflective elements disposed on a substrate and each of the reflective elements are capable of structural change into one of a plurality of stable states wherein each of the reflective elements maintains a stable optical property. A computer selectively controls the state of the array of reflective elements to thereby cause each reflective element of the array to selectively reflect incident light such that the array of reflective elements can generate a desired holographical or optical image.Type: GrantFiled: May 5, 2003Date of Patent: November 16, 2004Inventor: Igor M. Koba
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Patent number: 6816561Abstract: An apparatus for processing data includes a first processor and a second processor. The first processor receives a source clock signal and converts the source clock signal to a first timing signal with a first phase. The second processor receives the source clock signal and converts the source clock signal to a second timing signal with a second phase. A phase connection circuit coupled to the first processor and the second processor determines whether the first phase is equivalent to the second phase. If the first phase and the second phase are not equivalent, the first processor will modify the first phase such that the first phase and the second phase are equivalent. The first processor may modify the first phase by inverting the first timing signal or by adding a clock delay to the first timing signal.Type: GrantFiled: August 4, 2000Date of Patent: November 9, 2004Assignee: 3Dlabs, Inc., LtdInventor: Michael Potter
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Patent number: 6801982Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.Type: GrantFiled: January 24, 2002Date of Patent: October 5, 2004Assignee: International Business Machines CorporationInventors: John M. Borkenhagen, Brian T. Vanderpool, Lawrence D. Whitley
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Patent number: 6783456Abstract: The present invention provides methods and systems for interactively playing a lottery-type game among a number of players. In one embodiment, this is accomplished on a network of gaming terminals in communication with a central controller. An objective of the game is for a player to select the number closest to the randomly selected number that represents the winning number for the lottery game. This is a significant departure from the prior art, in that the game of the present invention does not require an exact match to produce a win and in that the game results in a win for every drawing. Thus, the lottery-type game of the present invention improves the gaming experience for the player, which will result in prolonged and more frequent play, thereby maximizing revenues for the operator of the game.Type: GrantFiled: December 19, 2001Date of Patent: August 31, 2004Assignee: Scientific Games Royalty CorporationInventor: Michael L. White
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Patent number: 6775411Abstract: An apparatus, method and computer program for recognizing one or more images within digitized image data that might include a target image desired to be located. The system generates a set of domain blocks from the image data where each domain block represents a discrete portion the image data and a set of range blocks from one or more target images. Either the domain blocks, the range blocks, or both, are transformed by one or more substantially affine transformations with predetermined coefficients to create possible variants of the images. A comparison between the blocks is made to determine similarity, and includes at least a measurement of whether better matching is achieved when a range block is chosen from image data representing the image which is the source of the domain block or when chosen from other image data.Type: GrantFiled: October 18, 2002Date of Patent: August 10, 2004Inventors: Alan D. Sloan, Ruifeng Xie
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Patent number: 6765588Abstract: A system and method for generating random coverage masks for rendering images with transparent objects. The system uses shuffle tables for addresses of a pixel to index into a transparency table and to obtain a transparency mask, which is then ANDed with a coverage mask to obtain a new coverage mask.Type: GrantFiled: August 29, 2002Date of Patent: July 20, 2004Assignee: 3Dlabs, Inc., Ltd.Inventors: Dale L. Kirkland, James L. Deming
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Patent number: 6766324Abstract: A system, method, and computer program for the creation and implementation of configurable Java classes on a computer platform executing instructions based upon at least a set of Java language instructions. The configurable Java class is created as an instance of a metaclass object included within the set of Java language instructions, and the configurable metaclass object includes a plurality of subclasses and interfaces wherein each interface includes one or more methods to alter the attributes and methods of the Java class instance of the metaclass object. The metaclass object is preferably implemented as an Enterprise JavaBean.Type: GrantFiled: July 20, 2001Date of Patent: July 20, 2004Assignee: International Business Machines CorporationInventors: Brent Carlson, Valquiria Cristina da Cruz, Tim Graser, Mircea P. Marandici, Gary Joseph Pietrocarlo, Andre Tost, Craig Dean Woods, Ravindran Yelchur
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Patent number: 6766410Abstract: A system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the fragments are placed into a first and second data fragment buffer such that the data fragments are in sequential addresses whereby the second data read on the trailing edge of the clock cycle will read the proper data fragment.Type: GrantFiled: June 10, 2002Date of Patent: July 20, 2004Assignee: 3Dlabs, Inc., Ltd.Inventor: Stewart Carlton
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Patent number: 6751668Abstract: A method and apparatus for responding to denial of service attacks. Rather than a firewall or other device either denying all new session requests or denying no new session requests (and, albeit, dropping then-pending session requests), new session requests are selectively passed to the device.Type: GrantFiled: March 14, 2000Date of Patent: June 15, 2004Assignee: Watchguard Technologies, Inc.Inventors: YeeJang James Lin, Chung-Wen Soung
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Patent number: 6734860Abstract: An apparatus for processing a graphical data stream for display on a display device includes a processor, a first conversion module and a second conversion module. The processor determines the characteristics of the graphical data stream. The first conversion module and the second conversion module convert the graphical data stream in a first format to a second format. The graphical data stream is directed to the first conversion module by a first data path and the graphical data stream is directed to the second conversion module by a second data path. A switching system is used to alternately connect the first conversion module through the first data path and the second conversion module through the second data path.Type: GrantFiled: August 4, 2000Date of Patent: May 11, 2004Assignee: 3Dlabs, Inc., Ltd.Inventors: Michael Potter, Clifford A. Whitmore
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Patent number: 6732199Abstract: A system and method for scheduling packet output according to a quality of service (QoS) action specification. A system is provided with a calendar queue with a plurality of bandwidth timeslots, wherein the bandwidth timeslots are organized into groups. A look-up logic circuitry inspects a group of bandwidth timeslots substantially simultaneously and determines from the group a first unoccupied bandwidth timeslot in which a current packet can be scheduled. The look-up logic circuitry also determines a first occupied bandwidth timeslot that contains a next packet to be transmitted.Type: GrantFiled: December 16, 1999Date of Patent: May 4, 2004Assignee: Watchguard Technologies, Inc.Inventors: JungJi John Yu, Chih-Wei Chao, Fu-Kuang Frank Chao
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Patent number: 6700576Abstract: An apparatus and method for rendering a circle with a radius on a display device comprises (a) providing a set of vertex points; (b) selecting a subset of vertex points from the set of vertex points based on the radius of the circle; (c) scaling each vertex point in the subset of vertex points to produce scaled vertex points; and, (d) connecting the scaled vertex points to approximate the circle. The subset of vertex points may be utilized to determine scaled vertex points for all four quadrants of the circle. The subset of vertex points may be selected by determining the number of vertex points required to render the circle with an error less than a predetermined error threshold. The subset of vertex points is then selected so that the number of members in the subset of vertex points is equivalent to the number of vertex points required to render the circle with an error less than the predetermined threshold.Type: GrantFiled: March 24, 2000Date of Patent: March 2, 2004Assignee: 3Dlabs, Inc., Ltd.Inventors: William R. Lazenby, Jr., Dale Kirkland, Steven J. Heinrich
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Patent number: 6690369Abstract: A multiple-pass system for determining the primitives that are visible in a predetermined pick aperture for a “visible pick” operation. On the first pass, the primitives contained within the pick aperture and thus potentially visible are selected, and each selected primitive is assigned a pick index as an identifier. On the second pass, the pick indices of the selected primitives are rendered to a temporary frame buffer area, using a Z-buffer for hidden surface removal so that only the pick indices of the primitives visible within the pick aperture are stored in the corresponding frame buffer portion. On the third pass, the frame buffer portion corresponding to the pick aperture is read to determine the pick indices of the visible primitives. This information is then used to report back to the host the picked primitives.Type: GrantFiled: August 1, 1997Date of Patent: February 10, 2004Assignee: 3DLabs, Inc., Ltd.Inventors: George Randolph Smith, Jr., Karin P. Smith, David John Stradley
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Patent number: 6677954Abstract: A method for caching graphics-related data in one or more graphics request buffers wherein duplicative graphics-related data is not written to the graphics request buffers. In the preferred method the graphics-related data is sent in frames, and each frame contains frame setup data and graphical model data, and the model data is compared between the stored frame and the new frame to determine if there is new model data to be written to the graphics request buffers.Type: GrantFiled: November 8, 2001Date of Patent: January 13, 2004Assignee: 3Dlabs, Inc., LtdInventors: Allen Jensen, Dale Kirkland, Harald Smit
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Patent number: 6677802Abstract: An apparatus for biasing a body voltage of a silicon-on-insulator transistor includes an operational amplifier that generates an output voltage that is proportional to the voltage difference between a desired gate-source threshold voltage and a reference voltage. A reference biasing transistor has a gate that is electrically coupled to the output. A reference mirror transistor has both a gate and a drain that are electrically coupled to the current source node, and also has a body that is electrically coupled to the drain of the reference biasing transistor. A device biasing transistor has a gate that is electrically coupled to the output voltage and has a drain that is electrically coupled to the body of the silicon-on-insulator transistor. The device biasing transistor maintains a voltage at the body of the silicon-on-insulator transistor so that it has a gate-source threshold voltage within a predetermined range of the desired gate-source threshold voltage.Type: GrantFiled: September 5, 2001Date of Patent: January 13, 2004Assignee: International Business Machines CorporationInventors: James D. Strom, Patrick L. Rosno
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Patent number: 6674440Abstract: A method, computer program product, and graphics processor for stereoscopically displaying a primitive on a display device adds a row of pixels to the primitive to improve its appearance on the display device. To that end, it first is determined if the primitive is to be stereoscopically displayed on the display device. After it is determined that the primitive is to be stereoscopically displayed, then a row of pixels is added to the primitive. The primitive preferably is a point primitive or a line primitive.Type: GrantFiled: March 23, 2000Date of Patent: January 6, 2004Assignee: 3Dlabs, Inc., Inc. Ltd.Inventors: Dale Kirkland, James Deming
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Patent number: 6667744Abstract: A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.Type: GrantFiled: August 21, 2001Date of Patent: December 23, 2003Assignee: 3Dlabs, Inc., LtdInventors: Matt E. Buckelew, Stewart G. Carlton, James L. Deming, Michael S. Farmer, Steven J. Heinrich, Mark A. Mosley, Clifford A. Whitmore
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Patent number: 6667930Abstract: An enhanced checkerboard pattern for optimizing performance when accessing a four-bank SDRAM. The screen is mapped using the enhanced checkerboard pattern, and each enhanced checkerboard pattern is composed of 16 squares. The enhanced checkerboard is made from two basic blocks, each block having 4 squares, and each square representing a distinct memory bank. The two basic blocks are mirror image of each other.Type: GrantFiled: June 12, 2002Date of Patent: December 23, 2003Assignee: 3Dlabs, Inc., Ltd.Inventor: Stewart Carlton