Abstract: A system and method implemented in an interactive television system for restricting or controlling the access rights of interactive television applications and carousels. The system broadcasts modules from a broadcast station to a plurality of receiving stations, which execute applications containing the modules. In one embodiment, the applications utilize a credential consisting of a producer identification number (ID) and an application ID for each of the grantor and grantee applications, an expiration date, a set of permission data, a producer certificate and a signature. An application requesting access and a carousel granting access may be identified by respective producer and application IDs. The credential utilizes public key encryption to ensure the integrity of the credential. The producer and application IDs may be replaced with wildcards so that rights may be granted to a group of producers or applications.

Abstract: An apparatus and method are presented for testing an adhesive layer formed between an integrated circuit and a plate, wherein the plate may be semiconductor device package substrate or a heat spreader. The apparatus includes a pull stud and a pull arm. The pull stud has an upper portion and a lower portion, wherein the lower portion is attached to a surface of the integrated circuit opposite the plate. The upper portion of the pull stud may be, for example, a tapered cylinder having a large end and a small end. The small end meets the lower portion of the pull stud. The pull arm has two opposed ends and at least one bracket for receiving a force. One of the pull arm ends has a "V"-shaped opening surrounded by a lip which receives the upper portion of the pull stud. During use, the lip contacts and retains the upper portion of the pull stud. The opening has an upper wall, and an upper surface of the pull stud contacts the upper wall when the upper portion of the pull stud is inserted into the opening.

Abstract: A phase-locked-loop circuit including a prescaler which divides the frequency of an output signal to thereby generate a frequency-divided signal which is provided as a feedback signal to a phase detector of the phase-locked-loop circuit. The prescaler includes a plurality of analog flip-flop circuits serially connected in a chain, with one or more outputs of latter analog flip-flop stages in the chain being fed back to one or more inputs of the first analog flip-flop. Embedded logic is integrated with the differential input pair of the first analog flip-flop to conditionally control the output of the first analog flip-flop based upon the feedback signals from the latter flip-flop stages. The analog flip-flop with embedded logic includes a master section for setting a state of a differential set up signal in response to an occurrence of a first phase of a clock signal.

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump.

Abstract: A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at a higher clock frequency. Each of the devices resident on the PCI bus include certain configuration registers, including MIN.sub.-- GNT and MAX.sub.-- LAT, which provide configuration parameters to various system resources. In addition, each of the devices resident on the PCI bus include a status register with a dedicated 66 MHzCAPABLE bit. The dedicated status bit indicates whether the PCI device is capable of operating in a 66 MHz environment. As a result, each device can be polled during system initialization to determine if all of the PCI devices will support 66 MHz operation. If the system determines that the clock frequency will change due to a change in the system configuration (such as PCI devices being added or removed from the PCI bus), the configuration registers of each of the PCI devices can be modified to insure proper operation at the new clock frequency.

Abstract: An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The early address generation units may be successful at generating the data address if the logical data address is formed from a displacement only. Additionally, the early address generation unit may be successful at generating the data address if the logical data address is formed from the displacement and register operands which are available upon decode of the instruction. Data address generation latency may be shortened. If register operands are employed for forming the address and the register operands are not available, the data address may be generated in a functional unit at the execute stage.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift, and correcting I/Q angular error and amplitude imbalance. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which digitally performs I/Q angular error correction. The tuner converts the high frequency signal to a baseband signal having an in-phase and a quadrature-phase component. Ideally, the components are separated by ninety degrees, but typically an angular error exists. The demodulator/decoder includes an adaptive equalizer for correcting the angular error. Having the equalizer allows for relaxed tolerances in the tuner.

Abstract: A method and apparatus for software to access a microprocessor serial number. Provision of the serial number allows the manufacturer better control over its product and also permits software vendors to register their products. The serial number is encrypted using a pair of encryption keys to prevent unauthorized changes. At least one of the encryption keys is itself encoded to prevent unauthorized access, while permitting software to access the serial number.

Abstract: A dependency checking method includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an indication within the scoreboard. Each double precision register which does not overlap with single precision registers maps to an indication within the scoreboard. Double precision registers which overlap single precision registers map to the set of indications corresponding to the overlapping single precision registers. Dependency checking for a source operand is performed by forming a first set of indications corresponding to the double precision registers and a second set of indications corresponding to the single precision registers, then selecting a dependency indication from these sets of indications in response to the source precision and the source register address.

Abstract: A microprocessor employing an apparatus for performing special register writes without serialization is provided. The apparatus detects special register write instructions when the instructions are dispatched, and stores an indication of the write in a special register dependency block. Instructions subsequent to the special register write instruction are examined for both explicit and implicit dependencies upon the special register write. If a dependency is detected with respect to a particular instruction, the instruction is dispatched to a reservation station along with an indication of the dependency. Instructions subsequent to the special register write instruction which are not dependent upon the special register are dispatched without an indication of special register dependency. Instructions without dependencies may speculatively execute prior to instructions with dependencies, or even prior to the special register write instruction.

Abstract: A dependency checking apparatus includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an indication within the scoreboard. Each double precision register which does not overlap with single precision registers maps to an indication within the scoreboard. Double precision registers which overlap single precision registers map to the set of indications corresponding to the overlapping single precision registers. Dependency checking for a source operand is performed by forming a first set of indications corresponding to the double precision registers and a second set of indications corresponding to the single precision registers, then selecting a dependency indication from these sets of indications in response to the source precision and the source register address.

Abstract: A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions.

Abstract: The present invention permits a primary launch engine to display the names of, and information relating to, and cause the execution of diagnostic/test programs and/or batch-type routines for the silicon validation of microprocessors not only in existence at the time the primary launch engine is developed and compiled, but also, diagnostic/test programs and/or batch-type routines for the silicon validation of microprocessors that are developed and/or modified after the primary launch engine is developed and compiled without requiring modifications to, or the recompilation of, the primary launch engine. To do so, the present invention utilizes specialized data files consisting of one or more screen definition files and/or one or more script files wherein each screen definition file contains necessary menu structure and response information for each of the available diagnostic/test programs and wherein each of the script files contains sequencing and parameter information for each of the batch-type routines.

Abstract: An improved bus arbitration system comprising an information bus, first and second bus masters connected to the bus and a bus arbiter for controlling ownership of the bus. The first bus master is adapted to perform speculative pre-fetching and has a first REQ signal for requesting ownership of the bus and an SP signal for indicating when a bus ownership request is for a speculative pre-fetch. The second bus master has a second REQ signal for requesting ownership of the bus. The bus arbiter is configured such that when the first bus master asserts its REQ signal and its SP signal and the second bus master asserts its REQ signal, the bus arbiter assigns higher priority to the second bus master in response to the SP signal.

Abstract: A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the retrieved data values, if necessary, to place them in the proper order for the processing array. The address decoder provides a select value to the select logic and a shift value to the shift network for each cycle. For purposes of horizontal decimation, the pixel values are organized into an even and an odd group, which groups are stored in the memory buffer in two separate regions separated by an address offset K.

Abstract: A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Upon system reset, the BIOS boot code reads a configuration register MAXLAT within each alternate bus master. The contents of the configuration register are indicative of how often the particular master may require access to the peripheral bus. Upon reading the MAXLAT field of each master, the system sets a timer in accordance with the MAXLAT value corresponding to the master which requires the most frequent access to the peripheral bus. If the master requiring the peripheral bus most frequently specifies a maximum latency time of, for example, 2 microseconds, the system sets the timer to cycle (or trigger) every one microsecond (i.e., one-half of the specified maximum latency time).