Abstract: A memory device (10) includes switching circuitry 22 comprising sensing and control circuits (24 and 26) to predict the next state of the output of memory device (12) and to turn on and off current sources (20) responsive to said memory output to provide faster output transitions.

Abstract: A method for polishing the edges of a plurality of semiconductor wafers rotates a stack of wafers against a polish one or more pads such that both the wafer edges and the sides of the edges are polished to a mirror finish. The polish pad has a series of grooves through which the wafer edges are passed to polish the sides of the wafer edges, or two pads are used, one with grooves and one without grooves.

Abstract: A pointer for a three dimensional display utilizes sensors on the display for the user to communicate with the display by means of a hand held device. The three dimensional display can have a spatial light modulator with a plurality of deformable mirror cells each with several memory cells.

Abstract: A disposable integrated circuit test head (34) communicates a plurality of test signals between test nodes (20) of an integrated circuit and test circuitry. Disposable high-density test head (30) comprises signal platform (24) which includes tape layer (24) and interconnection lines (28). Interconnection lines (28) include signal leads (30) and bumps (32). Interconnection lines (28) coupled with test nodes (20) to electrically connect test nodes (20) with the test circuitry and communicate test signals between test nodes (20) and the test circuitry. Pusher block (36) engages signal platform (24) at tape layer (26) opposite interconnection lines (28) and applies force through tape layer (24) to interconnection lines (28). This allows positive engagement of interconnection lines (28) with test nodes (20). Pusher block (36) comprises rigid force applying plate (38) which adheres to compliant layer (40) at junction (42).

Abstract: Circuitry for actively reducing the effects of ground voltage fluctuations in integrated circuits is described. An input buffer circuit including an output transistor 30 is provided along with a compensation circuit that is designed to reference the base of transistor 30 to an internal ground node of the integrated circuit. The compensation circuit includes a control diode 46, compensation transistors 42 and 43, bias resistors 40, 41 and 45 and diode chain 47, 48 and 49. In operation, the compensation circuit prevents the undesirable switching of output transistor 30 under low input voltage conditions by actively coupling the base of transistor 30 to internal ground through two conducting compensation transistors 43 and 42. Under these conditions, control diode 46 remains reverse biased allowing current flow through diode string 47, 48, and 49 which establish a threshold voltage to set the level at which compensation transistor 43 turns on.

Abstract: A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both.

Abstract: Disclosed is a burn-in test socket which serves as a temporary package for integrated circuit die, multichip hybrid or a complete wafer without damaging the bonding pads or insulating passivation on the die during test and burn-in.

Abstract: A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: A circuit for the Class-A differential amplification of two input signals.A first constant current source 22 is connected between a voltage supply terminal 3 and a node 8. A second constant current source 24 is connected between the supply terminal 3 and a node 9. A first transistor T1, with a control electrode connected to input terminal 1, has a conduction path connected between node 8 and a voltage supply terminal 10. A second transistor T2, with a control electrode connected to input terminal 2, has a conduction path connected between node 9 and terminal 10. A third transistor T3, with a control electrode connected to input terminal 1, has a conduction path connected between node 9 and an output terminal 6. Finally, a fourth transistor T4, with a control electrode connected to input terminal 2, has a conduction path connected between node 8 and an output terminal 7.

Abstract: Disclosed is a monolithic magnetic integrated circuit. A magnetic material (22) is formed on a semiconductor substrate (10) in multiple layers to form a closed circuit. The closed circuit magnetic material (42) is formed around a deposited conductor (32) which is insulated from the magnetic circuit by silicon dioxide (34).

Abstract: A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly therefrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semicondcutor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).

Abstract: An apparatus and method for inspecting coatings on the surface of an object includes a light source of a ring light to uniformly light an object that is placed inside a diffusing view chamber. A video system measures the reflected light intensity from the surface of the object to determine if there are voids in the surface coating.

Abstract: An output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18, 20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N channel and P channel transistors having their gates connected to V.sub.cc and ground respectively. The amount of current control may be adjusted to compensate for environmental conditions such as temperature or voltage supply either dynamically or prior to use.

Abstract: A voice coil actuated wire tensioner is used on a wire bonder in conjunction with a primary wire clamp to provide accurate control of the bond wire and looping of the bond wire between ball bonding of one end of a bond wire and stitch bonding of the other end of the bond wire.

Abstract: A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.

Abstract: An amplifier includes an input circuit for alternately selecting input signals to be compared and a first bias circuit for producing self-bias when one of the input signals is selected. A second bias circuit stores the self-bias for use in the amplifier when the other of the input signals is selected for rejecting noise which may accompany power supply voltage applied to the amplifier.

Abstract: A threshold detection circuit (10) is provided which comprises an input node (12) and an output node (14). The input node (12) is coupled to a current mirror (22) through a resistor (32). The current mirror (22) is further coupled to another current mirror (16), which is arranged to receive a reference current proportional to absolute temperature. The reference current is mirrored and, having been increased by a multiplier is received by a current sink (28). When the voltage level at the input node (12) exceeds a predetermined voltage threshold level, the current exceeding the amount sinkable by the current sink (28) is directed to the base of a switching transistor (30) coupled to the output node (14), and produces an output voltage level at the output node (14) indicative of the threshold voltage level being reached an/or exceeded at the input node (12). The predetermined threshold voltage may be at a level exceeding the circuit supply voltage level and is independent of ambient operating temperature.

Abstract: A charge pump comprises high voltage and low voltage supply rails coupled to first and second capacitors via switching circuitry. The switching circuitry is operable to charge the first and second capacitors to desired voltages to generate a desired output voltage of increased magnitude.

Abstract: Reaction gases are prevented from escaping from a reaction chamber through the use of flexible or gas seals between the interface of the reaction chamber and the junction used to connected successive reaction chambers.

Abstract: A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.