Patents Represented by Attorney, Agent or Law Firm Beall Law Offices
  • Patent number: 6335103
    Abstract: A magnetic recording medium including a substrate and a magnetic layer on the substrate which is a Co-based alloy including Pt and/or Ir, including at least one of Ti, Zr, Hr, V, Nb, Ta, Cr, Mo, W, Ge, and Si, and including oxygen. A magnetic memory apparatus including the magnetic recording medium.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: January 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Suzuki, Yoshihiro Shiroishi, Sadao Hishiyama, Tomoyuki Ohno, Yotsuo Yahisa, Yoshibumi Matsuda, Norikazu Tsumita, Masaki Ohura, Takaaki Shirakura, Noriyuki Shige, Kazumasa Takagi
  • Patent number: 6205535
    Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 6190424
    Abstract: A semiconductor integrated circuit device fabrication method has a main processing line and a sub-processing line. The main processing line includes a plurality of main batch processing sections, each of which processes a plurality of main objects at a time, and a plurality of main sequential processing sections, each of which processes a minimum number of main objects at a time. The main processing line feeds the main objects to the main batch processing sections and the main sequential processing sections for predetermined processing. The sub-processing line includes a plurality of sub-processing sections, each of which performs processing identical with that of a corresponding main batch processing section on a minimum number of sub-objects and certain of the main sequential processing sections. The sub-processing line feeds the sub-objects to the sub-processing sections and the main sequential processing sections for predetermined processing.
    Type: Grant
    Filed: January 11, 1995
    Date of Patent: February 20, 2001
    Assignee: Hitachi, Ltd.
    Inventor: Atsuyoshi Koike
  • Patent number: 6180020
    Abstract: The present invention relates to a polishing method using a grindstone comprising abrasive grains and a bonding resin for bonding the abrasive grains, as well as to a polishing apparatus to be used for the polishing method. By using a resin for bonding abrasive grains, it is possible to obtain a grindstone having a desired modulus of elasticity. With such a grindstone, the surface of a substrate having concave and convex portions can be rendered uniformly flat, irrespective of the size of the concave and convex portions. Further, by first polishing the substrate surface with a polishing tool of a small elastic modulus and thereafter polishing it with a polishing tool of a large elastic modulus, it is possible to obtain a polished surface of reduced damage. The method of the invention is effective in planarizing various substrate surfaces having concave and convex portions.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: January 30, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Moriyama, Katsuhiko Yamaguchi, Yoshio Homma, Sunao Matsubara, Yoshihiro Ishida, Ryousei Kawa-ai
  • Patent number: 6172363
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: January 9, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
  • Patent number: 6169948
    Abstract: A setting device for a front control system for a construction machine includes a direct setting switch for instructing a direct teaching setting, a numeral input key consisting of up- and down-keys for instructing a numeral input setting, a setting changeover switch for changing over a setting mode from the direct teaching setting to the numeral input setting, an LED lighting up when the setting changeover switch is pushed, an area limiting switch for starting an area limiting excavation control, an LED lighting up when the area limiting switch is pushed, and a display screen for indicating the position of a bucket end of a front device in terms of a numeral value when the setting changeover switch is not pushed, and indicating the numeral value input with the numeral input with the numeral input setting when the setting changeover switch is pushed.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: January 2, 2001
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Kazuo Fujishima, Hiroshi Watanabe, Masakazu Haga, Takashi Nakagawa
  • Patent number: 6163186
    Abstract: A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: December 19, 2000
    Assignee: Hitachi, Ltd.
    Inventor: Kozaburo Kurita
  • Patent number: 6157203
    Abstract: A semiconductor integrated circuit including an input circuit constituted as a single-input differential circuit which has a first MOSFET to whose gate a reception signal with a small amplitude with respect to a power supply voltage is supplied and a second MOSFET to whose gate a reference voltage corresponding to an intermediate value of the reception signal is supplied. A dummy circuit is provided and transmits substantially the same power supply noise as the power supply noise transmitted to the gate of the first MOSFET through a electrostatic protection circuit provided to an external terminal which receives the reception signal.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: December 5, 2000
    Assignee: Hitachi, Ltd.
    Inventor: Toshiro Takahashi
  • Patent number: 6153357
    Abstract: Herein disclosed is an exposure technology for a semiconductor integrated circuit device which has a pattern as fine as that of an exposure wavelength. The technology contemplates to improve the resolution characteristics of the pattern by making use of the mutual interference of exposure luminous fluxes.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: November 28, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiko Okamoto, Noboru Moriuchi
  • Patent number: 6147001
    Abstract: A method of manufacturing a semiconductor integrated circuit wherein a patterned wafer polishing machine for uniformly polishing a surface by chemical mechanical polishing is utilized which is provided with a head for holding a wafer and rubbing it on an abrasive surface. A pressure plate provided with vents is held by the head body which is provided with a gas inlet and an elastic film for sealing vents is provided on the end face on the side reverse to the gas inlet side of the pressure plate. A patterned wafer is held by the head as the wafer, pressed by action of the pressure of air from the gas inlet via the elastic film is pressed mechanically by the pressure plate. The polishing surface which is a principal plane on the patterned side of the wafer is mechanochemically polished by the abrasive surface.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: November 14, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Kimura, Hidefumi Ito, Hiroyuki Kojima, Nobuhiro Konishi, Yuuichirou Taguma, Shinichiro Mitani
  • Patent number: 6144005
    Abstract: A vacuum insulation switch provided with a movable electrode, a stationary electrode and an earthing electrode, which are insulated from each other, in a vacuum container made of a conductive material which is earthed, and a switchgear using the same.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: November 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Toru Tanimizu, Masato Kobayashi, Shuichi Kikukawa, Ayumu Morita, Minoru Suzuki, Yoshimi Hakamata, Katsunori Kojima, Yozo Shibata, Yoshitomo Gotoh, Makoto Terai, Takuya Okada, Naoki Nakatsugawa
  • Patent number: 6144956
    Abstract: In a DB retrieval method, a two-step retrieval including quantitative and qualitative retrievals is interactively performed so that, through the operation of image information (e.g. map information) having a correspondence to a DB having text information such as attribute information stored therein, attribute information corresponding to the map information is retrieved from the DB. The quantitative retrieval includes a DB information reading process for reading image information, attribute information and information relevant thereto, and a quantitative retrieval process for making a quantitative retrieval including the partial overlaying of another information for retrieval on the original image information (or map information) or a rough retrieval with the other information used as a retrieval key called information lens, and storing the result of retrieval into a work file.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: November 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yajima, Hiroyuki Okuda, Noritsugu Kagaya, Maki Tamano, Shunsuke Akifuji
  • Patent number: 6141016
    Abstract: On a computer, components forming a development subject are arranged on a scenario editor by using basic component parts, and the component data are set. And a procedure call sequence is defined by specifying procedures of defined components in order of call. The call sequence data is generated in the computer as scenario data. Then, the defined group of scenarios are selected and reflected on the model editor. A whole requirement is created. At that time, a procedure name to be called subsequently on the connection line between components is acquired from the defined procedure sequence data, and a program for effecting animation is generated. Finally, by executing the generated animation program, the procedure call sequence is displayed in an animation form and the requirement is created.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: October 31, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiko Yuura, Hisashi Takahashi
  • Patent number: 6137786
    Abstract: In CDMA communications, a base station detects a difference between a reference phase of a spreading code and a phase of a received signal of each terminal station, and feeds a phase jump signal PJ-i representative of the phase difference back to each terminal station. After timing acquisition, the reception operation is performed using the reference phase, and a shift amount between the phase of a received signal and the reference phase is fed back to each terminal station as phase synchronization control information PC-i. Each terminal station coarsely adjusts the phase of the spreading code in accordance with the phase jump signal PJ-i, and thereafter finely adjusts the phase of its transmitting signal in accordance with the phase synchronization control information PC-i. It is therefore possible to synchronize the phases of the signals transmitted from terminal stations and received at the base station. Accordingly, an orthogonal code is used for spreading on the reverse links.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: October 24, 2000
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Masayuki Ariyoshi, Nobukazu Doi, Tesshin Shiga, Yoshito Ohta
  • Patent number: 6137185
    Abstract: An electrode structure as well as the fabrication method thereof is disclosed which may enable successful pad layout conversion of interconnection electrode pads on the periphery of an associated IC chip to a grid array of rows and columns of terminal solder pads arranged occupying the entire area of the opposite surface of the chip while permitting use of a minimized length of wire leads for interconnection therebetween.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: October 24, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Ishino, Ryohei Satoh, Mamoru Mita
  • Patent number: 6134203
    Abstract: An optical disk signal processing apparatus retains compatibility with the conventional continuous servo recording technique, and reduces the amount of noise included in a signal played back from the optical disk without the need to decrease the size of the area for recording data, resulting in a drastically increased signal-to-noise ratio. The optical disk signal processing apparatus has a light source, an optical system for leading a light beam generated by the light source, an optical device for converging the light beam output by the optical system and applying the converged beam to the rotating optical disk, a signal detecting optical system for detecting a signal reflected by the rotating disk through the optical device, and a light detecting instrument for converting light produced by the signal detecting optical system into an electrical signal and a data detecting circuit.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: October 17, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Maeda, Hisataka Sugiyama
  • Patent number: 6133135
    Abstract: The process for manufacturing an electronic circuit includes disposing an electronic device on a circuit substrate and hot melting a solder formed on the electronic device or the circuit substrate to bond the electronic device and the circuit substrate. The process includes the steps of feeding a liquid onto lands on the circuit substrate, aligning and mounting the electronic device on the lands, placing the circuit substrate in a treating vessel and heating the circuit substrate. The heating step includes controlling a pressure of an atmosphere in the treating vessel, hot-melting the solder to prevent at least a portion of the liquid from evaporating until the electronic device and the circuit substrate are bonded and to permit the liquid to evaporate after the electronic device and the circuit substrate are bonded.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: October 17, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kaoru Katayama, Hiroshi Fukuda, Shinichi Kazui, Toshihiko Ohta, Yasuhiro Iwata, Mitsugu Shirai, Mitsunori Tamura
  • Patent number: 6131142
    Abstract: With respect to the disk drives provided power from a single power source in a disk drive system, start up power is first supplied to a first start-up group of the disks, preferably comprising all of the master disks, with the size of the group being selected so that the required current does not exceed the capacity of the power source. When the disk drives of the first group have substantially reached steady state, start-up is conducted with respect to a second start-up group of the disk drives so that the current required during start-up for the second group and the current required for steady state drive of the first start-up group does not exceed the capacity of the power source. With respect to each start-up group, the number of disk drives is the maximum integer value and decreases or remains the same with respect to subsequent start-up groups.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: October 10, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Kamo, Hitoshi Kakuta, Atsushi Tanaka, Yosuke Seo
  • Patent number: 6130577
    Abstract: In a digital demodulator for phase modulated signals, logical values of a waveform-shaped phase-modulated signal are sampled based on a clock signal having a period that stands in integer ratio relationship to a carrier period of the modulated signal and thereafter subjected to serial/parallel conversion for each predetermined interval, whereby a logical pattern of a digital code train subjected to the serial/parallel conversion is analyzed. As a result, phase information required to demodulate digital data can be logically detected.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 10, 2000
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Yuko Tamba, Taiji Kondou, Katsuhiro Furukawa, Yukihito Ishihara
  • Patent number: 6131177
    Abstract: A system with a ferroelectric memory has a low probability of soft error thereby decreasing the possibility of serious damage to the system that might result from soft errors. The ferroelectric memory is provided with an overwrite-inhibited memory block 122 for storing the OS (Operating System) and applications, and an overwrite-free memory block 123 which is a work area. The overwrite-inhibited memory block 122 includes a parity bit storage 125. A process for checking and correcting error performed about once a day. A command for starting the error checking and correcting procedures is triggered by a switch such as power source switch. When an error occurs in the ferroelectric memory 120, it is possible to recover the function of the system.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: October 10, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kan Takeuchi, Hiroyuki Tanikawa