Abstract: A system and method for providing a constant electric field that is insensitive to fluctuations in the power supply to a FLASH EPROM during erasure. The system comprises a plurality of sector source drivers and a power supply insensitive constant current source. Each sector has at least one binary storage element. Each storage element has a source. The sector source drivers couple the at least one source of a sector to be erased to the power supply insensitive constant current source. The power supply insensitive constant current source provides an electric field across the tunneling oxide which is constant and insensitive to fluctuations in the power supply. This improves the wear characteristics and lifetime of the binary storage elements. In addition, this system remedies problems associated with short channel effects, electron trapping, and the use of various voltage sources.

Abstract: A recovery system for a power supply. The inventive system includes a first circuit which detects a reapplication of wall power to the power supply and generates a signal in response thereto after an interruption in the output thereof. A second circuit then automatically reactivates the power supply on receipt of the signal without operator intervention. The invention is particularly well suited for systems having multiple power supplies each operating within an associated power boundary. In this case, a first power supply provides power to a first load and a second power supply provides power to a second load. A control circuit is provided in each load. The control circuit is equipped to receive the signal indicating a reapplication of power to a power supply within another power boundary and automatically reactivate the power supply.

Abstract: A method and system in accordance with the present invention overcomes the problem of program applications causing an overcommitment of a performance resource, while permitting full use of the performance resource by multiple concurrent applications. In such a method and system each program whose applications need access to a specific performance resource subscribe to a particular protocol to dynamically manage the available performance resource. This permits full use of the performance resource by all of the applications in the system without risk of overcommitting all the performance resource.

Abstract: A multiprocessor system provides for a restartable stop condition that is fast and easily implemented. The multiprocessor system includes a plurality of processors. Each of the processors includes a bidirectional stop pin, which normally when asserted indicates that an error has been detected. Each of the plurality of processors also includes a scan port. The plurality of processors in the multiprocessor system are coupled together via their respective stop pins. By switching the stop pins to a different mode whereby an assertion of the pin causes the receiving processor to enter a restartable stop condition as a result of a restartable stop condition being achieved by the driving processor, the multiprocessor system can be quickly stopped.

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

Abstract: A clock edge regulator that adds precision midcycle edge timing to an existing clock distribution. Two phase detector and phase delay pairs regulate the rising and falling clock edges. The falling edge is regulated to a precision time interval division of the clock period to provide an accurate duty cycle for the clock distribution.

Abstract: A smooth, seamless arcuate-shaped inside corner is formed between a counter top and a splash board, both made from a filled polymer material. The counter top has a top surface, while the splash board has an end edge orthogonal to a front surface. The two articles are joined to form a butt joint therebetween, and a bead of a filled epoxy material is formed along the inside corner of the butt joint. A smoothing tool, which has a smoothing surface of the desired curvature, is used to smooth the bead. When cured, the bead matches the color and texture of the two articles and provides a smooth, seamless, arcuate-shaped inside corner. The filled epoxy comprises an epoxy resin and a hardener in a ratio of about 2:1 resin:hardener, together with a filler and/or a colorant. The filler comprises a mixture of alumina trihydrate and particulates in a ratio within the range of about 75:25 to 25:75 alumina trihydrate:particulates.

Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.

Abstract: A performance diagnosis system (PDS) is utilized to analyze, diagnose and provide reports concerning the operation of a computer system. The PDS includes a system model database that contains historical and configuration information which is received on a periodic basis from resource managers within the computer system. The information is updated on a regular basis by individual collectors which are coupled to the resource managers. A reporter receives the historical and configuration information from the database to provide reports on different aspects of the performance of the computer system. In addition, different types of assessments of performance of the computer system is provided by the PDS.

Abstract: A system and method is disclosed for increasing read performance of domino SRAMS. A conventional word-line, which drives two transistors per cell, is replaced with two separate word-lines. The first word-line drives one transistor and the second word-line drives the other transistor. The first word-line is used to write zeros into cells, while the second word line is used to both write ones into cells and to read the contents of the cells. Since the second word-line drives only one transistor during read operations, one-half of the gate load on the writeead word-line is eliminated.

Abstract: A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size.

Abstract: A process is provided for forming a hard mask over an aluminum-containing layer for patterning and etching the aluminum-containing layer to define interconnects. The process comprises depositing the material comprising the hard mask at a temperature that is within the range of about 100.degree. C. below the sputtering temperature of the aluminum-containing metal and the sputtering temperature of the aluminum-containing metal.

Abstract: Novel multiplexed volume holographic optical elements for the development of highly multiplexed photonic interconnection and holographic memory systems with maximum optical throughput efficiency and minimum crosstalk, based on parallel incoherent/coherent double angularly multiplexed volume holographic recording and readout principles, are disclosed. These principles further provide for arbitrarily weighted and independent interconnections, which are of potential importance in the development of densely interconnected photonic implementations of neural networks, photonic interconnection networks for telecommunications switching and digital computing applications, optical information processors, and optical memories. Utilization of the principles that are key features of this holographic element allows for the single step transfer of all or part of the information stored in a three-dimensional holographic storage device to a second such device in a single exposure step.

Abstract: A method and apparatus is disclosed for recovering data with unstable low amplitude magnetorestrictive heads. After an error in data recovery is detected a technique is invoked that changes the bias current through the magnetoresistive head to the reverse direction in a predetermined manner. The method includes reversing the bias current direction, returning the bias current to its normal state and reading the data from the storage medium. Alternatively, the method includes reversing the bias current direction and reading the data when the bias current direction is reversed.

Abstract: A system and method for providing an optical isolator comprising a first collimating means, a core, and a second collimating means is disclosed. The first collimating means comprises at least a first optical fiber holder, a first lens, and a first collimator holder. The core comprises a first polarizer, a polarization rotation means, and a second polarizer. The second collimating means comprises at least a second optical fiber holder, a second lens, and a second collimator holder. One aspect of the method and system provides a quartz collimator aligner in a collimating means. The quartz collimator aligner aligns the optical fiber holder and the lens. The collimator holder is disposed around the quartz collimating aligner. The quartz collimator aligners improve the alignment of the collimator, thereby reducing insertion loss. The smoothness quartz collimator aligners also increases return loss.

Abstract: A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.

Abstract: A method and means for asynchronous remote data duplexing at a distant location from copies based at a primary site storage subsystem in which there are first and second pluralities of subsystems at primary and remote sites respectively. Each of the first plurality of subsystems is independently coupled to one or more of the second plurality of subsystems. Further, the first plurality of subsystems is interconnected, and the second plurality of subsystems is interconnected. The method utilizes checkpoint messages to maintain sequence integrity between the first and second plurality of subsystems without the use of a centralized communications service.

Abstract: A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.

Abstract: In one aspect of the present invention, a method includes the steps of providing a first test cell electrically isolated from the substrate, unexposed to the SAS etch and having a first core profile. The method further includes providing a second test cell electrically isolated from the substrate, exposed to the SAS etch, and having a second core profile. Additionally, the method includes performing the SAS etch, measuring electrical characteristics of the first and second cells, and comparing the measured electrical characteristics to determine an amount of gouging. In a further aspect of the present invention, a method includes the steps of forming a pair of test structures in electrical isolation of a substrate of the cell, and measuring resistance values for each of the pair of test structures to determine the amount of gouging. In addition, the method includes protecting one of the pair of test structures from the SAS etch.