Abstract: A method of speeding up computer simulation/emulation of circuit logic designs. The method converts an original circuit logic design (intended for hardware packaging) to a different circuit form before starting computer simulation/emulation. The converted circuit form provides the same simulation/emulation results as would have been obtained with the original logic circuit. The method operates with multi-phase logic designs comprised of gate circuits using multi-phase clocking of the type commonly packaged in semiconductor chips. The method converts such multi-phase logic designs into a single-phase circuit form, which is presented to the computer for simulation/emulation that provides the same results as the multi-phase logic design but at a much faster speed. The method is presented with a multi-phase logic design containing flip-flops as the internal storage circuits.

Abstract: I/O control unit (CU) features for supporting multiple host operating systems (OSs) which use missing interrupt handler (MIH) timeout functions for detecting potential failures of requested I/O device operations. These CU features support multiple host OSs by preventing them from falsely indicating I/O device failures, when in fact the device has not failed but is merely processing one or more other requests for other host Oss.

Abstract: Provides data and program integrity in a computer system by guarding against malicious program operation when using the Branch In Subspace Group instruction (BSG) of the S/390 computer architecture. System integrity is ensured by providing a controlled target space (a base space) and branch address during a BSG transfer of control (branch) from a subspace, and a different PSW key mask (PKM) for the base space than for subspaces. More specifically, (1) the PKM is reduced and a new PSW access key is set during a BSG branch from the base space to a subspace, (2) the original PKM and access key and also a return address are saved in a secure data area during the same branch, and (3), during a branch from a subspace, the original PKM and access key are restored, and the branch is made to the return address (the controlled branch address) in the base space.

Abstract: Work units are identified, managed and reported on as a group or enclave. The dispatching priorities of the work units are separated from the address spaces executing the work units. Instead, the dispatching priorities are tied to the priority of the enclave allowing work units to be executed within an address space at a priority independent from the address space. Additionally, resources used by the work units are accumulated and allocated to the requestor of the work.

Abstract: A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage.

Abstract: Automatic machine methods and apparatus for determining which components of an I/O configuration are shared by other components of the configuration. The information can be obtained through the use of existing self-description facilities and unique identifiers. By noting which channel paths are used to obtain configuration-data records and examining the unique identifiers provided for each I/O items it can be determined which I/O devices are accessible through the same control unit, and which control units provide access to the same I/O device. Furthermore, by examining the unique identifiers provided, it can be determined which I/O subsystems and which control units or channel subsystems are accessible through the same dynamic switch and which dynamic switches provide access to the same I/O subsystem of channel subsystem.

Abstract: A method and system to eliminate service hardware previously provided with an adapter by providing a novel way to transfer its hardware service functions to a remote service hardware found elsewhere in a computer system, such as a mainframe. The transferred service controls include enabling the remote service hardware to control the updating of the adapter microcode; remotely control a recovery process for the adapter by remotely initializing its microcode, and remotely logging out and recovering from error conditions detected in the adapter; and remotely forcing a logout and recovery when the host OS detects a failure in the adapter. A standard I/O channel interface (optical or electronic) is provided between the adapter and an IOSS (Input Output Subsystem) of a computer system which has its own service processor element (SPE) used for servicing the computer system per se. The invention provides virtual service hardware for the adapter, but uses the SPE for its service hardware.

Abstract: A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity.

Abstract: An Internal I/O Facility (iIOF) having a general interface for executing I/O related applications in an Input/Ouput SubSystem (IOSS) of a computer system. IIOF applications are executed in the IOSS outside the scope of CPU applications executed under the operating system (OS) of the computer system. IIOF applications are allowed to use all facilities in the IOSS. An iIOF subchannel extension is provided for those subchannels which can execute an iIOF application. IIOF subchannel extensions contain interception control fields which determine if conventional processing for the subchannel by the IOSS is to be intercepted to execute an iIOF application. A front-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is taken from the IOSS work request queue. A back-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is to have status put on the IOSS interruption queue.

Abstract: Connects a host computer system (such as a mainframe or host server system) to a large multimedia (MM) distribution network having wide scalability without being limited by bandwidth constraints in the host system or in any multimedia controller for controlling "on demand" viewing of movies at a large number of set-top-boxes (STBs) with TV sets. Connected to the host system is a network distribution arrangement comprised of a plurality of multimedia (MM) adapters, each MM adapter containing a plurality of MM controllers, each MM controller being connected to a multiplicity of MM pairs, each MM pair being connected to the network for controlling a direct distribution of movies to a large number of STBs. Each MM pair includes a disk adapter and a network adapter connected by a common MM pair bus for transmitting disk data blocks directly to the STBs. The disk adapter controls and receives data from one or more disk devices. The network adapter sends the disk data to the network.

Abstract: A method and system for managing one or more coupling facilities in a data processing system. An active policy is used to control resources located in the coupling facilities. The active policy can be changed such that control of the resources can be altered. Compatible changes are made immediately and incompatible changes are made at a subsequent time. Recorded in the active policy and in the coupling facilities is information regarding the resources. When the information in the active policy is not in synchronization with the information in the coupling facilities, a reconciliation technique is performed. The resources in the coupling facilities can be modified but prior to the modification, the intended modifications are stored in the active policy.

Abstract: A method and device for correcting hardware errors without loss of resources while maintaining continuous operation of the computer system. Same method and device can be used for repair or addition of hardware parts to this system. The method and device can operate in a fault tolerant system which allows continuous service during the occurrence of a hardware failure or while parts are being repaired or added to the system. The method and device also use Hamming code to detect and correct all hardware failures, particularly a soft-soft uncorrectable error and a special uncorrectable error or a SUE.

Abstract: Execution of input/output operations is controlled by one or more suspend and/or resume mechanisms. Suspension of an input/output operation is accomplished by one of a number of mechanisms including, for instance, a START SUBCHANNEL instruction with execution limits, a SUSPEND SUBCHANNEL instruction with or without a suspension time limit, or a suspend subchannel channel command word with or without a suspension time limit. Subsequent to suspending execution of a channel program, execution can be resumed automatically or by issuing a RESUME SUBCHANNEL instruction with limits or a resume subchannel channel command word with limits.

Abstract: A LOCK PAGE instruction is provided for locking a page of real storage using a virtual address. The LOCK PAGE instruction includes an operation code which specifies the operation to be performed, a first operand which contains the value of the real address obtained during execution of the LOCK PAGE instruction and a second operand which contains the value of the virtual address of the page to be locked during execution of LOCK PAGE. LOCK PAGE enables an address page or a data page to be locked without requiring the entire address space to be locked. A page is locked when a lock control bit in general register 0 is zero, the page is valid in main storage and a lock bit located in a page table entry is zero. In addition to the above, the technique used by an operating system service for reclaiming a page of real storage is altered to intersect with the LOCK PAGE facility.

Abstract: A new approach to providing thousands of contacts between electronic packages and their next package level by use of small formed spring contact elements (SCE) retained within a interposer structure or soldered directly into a printed circuit board or onto the module is disclosed. Each contact element can be either a signal or power line and, for improved electrical performance, alternate both horizontally and vertically in an orthogonal grid such that no signalling is adjacent to another signal. The spring contact elements (SCE) have multiple cross-sectional shapes and are pre-formed for improved mechanical performance. A retainer contains the multiplicity of SCE while providing a air plenum for improved thermal performance.

Abstract: A method of performing Ziv-Lempel type data compression while preserving in the compressed records any sort ordering of the uncompressed records. The method assigns the necessary ordered numbering to the code words for character strings in a static compression dictionary even though the dictionary is structured so that all children of the same parent have sequential index numbering. The children of a parent are in collating sequence order, and adjacent children that are nonadjacent in the collating sequence have a conceptual epsilon entry between them, which entry represents a match on the parent and a direction in the collating sequence. Code words for actual children are formed by using a dictionary entry index to locate a translation table entry containing a code word. Code words for epsilon entries are formed by using an entry index for an actual child to locate a translation table entry and then adding or subtracting one to or from the code word in the entry.

Abstract: A method of manufacturing thousands of contacts between electronic packages and their next package level by use of small wires retained within a interposer structure or soldered directly into a printed circuit board or onto the module. Each wire can be either a signal or power connection. The wires may have multiple cross-sectional shapes compared to one another and are preformed before assemble into an array retainer. The retainers contain the multiplicity of wires and are used for additional process steps and as the final housing of the connector assembly.

Abstract: A method for coordinating phases of program execution within a data processing system. One or more program defined synchronization events are established. Each synchronization event is responded to by one or more programs to coordinate phases of execution. The operating system notifies the one or more programs when all responses are received. A next program defined synchronization event may be established after a response is received for a previous synchronization event.

Abstract: Enables any OS of plural OSs within any of plural logical-resource partitions (LPARs) of a CEC to use interpretive execution for synchronously-executable CHSC (channel subsystem call) commands. A CHSC command authorization mask (CCAM) is provided to control which CHSC commands are allowed to execute interpretively (with pass-through), and which commands are executed with hypervisor intervention (as all prior CHSC commands did). By enabling interpretive execution of those commands which can successfully operate with pass-through, significant system efficiency is obtained. And by disabling interpretive execution for a subset of CHSC commands (which are not allowed to execute with pass-through) potential system failures may be prevented. Thus, interpretive execution may be restricted differently among the OSs in a CEC. Novel CHSC command execution now handles multiple images of shared I/O resources by use of image identifiers, which could not be done before.

Abstract: Coupling execution of channel programs without central processing unit supervision controls data transfer between input/output devices through a main storage of a data processing system. In one embodiment, channel programs to be coupled are generated by a program running on a data processing system central processing unit. The channel program on the input subchannel includes channel commands referencing the output subchannel and operating to cause resumption of the output subchannel. The channel program on the output subchannel includes suspend channel commands directed to itself which correspond to the resume channel commands in the channel program on the input subchannel. In alternative embodiments values in channel commands can change values in, or reference, control blocks to effect execution of other channel programs.