Abstract: A multilayer printed circuit board and a corresponding fabrication method are disclosed, which circuit board achieves a relatively high degree of wiring density and a relatively high degree of wiring design freedom. These advantages are obtained in the inventive printed circuit board by electrically connecting power conductors or ground conductors using through holes. On the other hand, signal conductors in any two adjacent signal wiring layers are electrically connected using via holes extending only through an intervening electrically insulating layer. Preferably, the electrically insulating layer is a layer of photosensitive resin and the via holes are formed using conventional photolithographic techniques.

Abstract: A new fiber optic connector housing and a new fiber optic receptacle, both of which conform to a new standard proposed by the X3T9.3 committee of the American National Standards Institute, are disclosed. In addition, four accessory devices for electro-optic modules, each of which includes one or more essentially conventional plug frames which fit into either one or more conventional, individual fiber optic connector housings or the new fiber optic connector housing, are disclosed.

Abstract: A new apparatus for treating substrates with fluids, as well as a corresponding fluid treatment method, is disclosed. The new apparatus includes a new configuration of fluid jet injectors which substantially overcomes the problem of dragout, in which fluid impinged upon an area of a substrate is retained on that area, preventing fresh fluid from reaching the impinged area. This new configuration also avoids imposing torques on substrates, and substantially reduces the need for rollers and guides for transporting substrates.

Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au--Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.

Abstract: A process of manufacturing a flexible metallized polymer film cover which provides environmental protection of electronic assemblies such as circuit card assemblies which are susceptible to external environmental factors which can impede functional performance and reduce reliability. The use of a metallized polymer film in the form of a two layer film, with two intimately bonded layers one being electrically insulative and the other metallic, provides environmental and electrical protection of the enclosed assembly.

Abstract: A TAB (tape automated bonding) tape is disclosed which includes one or more openings, each adapted to receive a semiconductor chip, and electrical leads extending into each such opening. Significantly, this TAB tape also includes means for preventing a semiconductor chip, positioned within a tape opening, from being lifted toward a bonding tool as a result of electrical leads adhering to the bonding tool, when the bonding tool is used to bond contact pads on the semiconductor chip to the leads extending into the opening.

Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.

Abstract: An AC-coupled receiver is provided which allows data with long periods of no signal sent on a fiber optic bus to be received without the normally required preamble. The receiver provides a voltage signal which is AC-coupled to one side of a differential amplifier with a delayed voltage signal AC-coupled to the other input of the differential amplifier. If the time constant of the AC coupling network is much longer than the signal baud time, low-frequency variations at the two inputs of the differential amplifier will be nearly identical and the low frequency signals will effectively cancel each other.

Abstract: A method for altering an electrical connection in an electronic package including one or more semiconductor chips overlying, i.e., mounted directly onto, or mounted onto one or more modules which are mounted onto, a substrate such as a printed circuit card or printed circuit board, as well as the resulting electronic package, is disclosed. In accordance with a preferred embodiment of the inventive method, at least one plated, solder-filled hole in the substrate is drilled out to eliminate an unwanted electrical connection. A solder region, e.g., a solder ball, is inserted into the drilled out hole into contact with an electrically conductive member, e.g., an electrically conductive pin, extending from, for example, a module into the hole. A cylinder, including a central core of electrically conductive material, encircled by an annulus of electrically insulating material, is inserted into the hole.

Abstract: Method and product resulting therefrom of controlling the residual resistivity of an electrolessly deposited metal by first, calculating the mathematical relationship between the residual resistivity of the deposited metal and its rate of deposition and second, depositing said metal at a rate to produce a predetermined residual resistivity.

Abstract: A new fiber optic connector housing and a new fiber optic receptacle, both of which conform to a new standard proposed by the X3T9.3 committee of the American National Standards Institute, are disclosed. In addition, four accessory devices for electro-optic modules, each of which includes one or more essentially conventional plug frames which fit into either one or more conventional, individual fiber optic connector housings or the new fiber optic connector housing, are disclosed.

Abstract: An optical device for sensing marks carried on an area to be sensed of a medium, especially printed and/or handwritten patterns, is disclosed. Sensing of marks is accomplished by inclined illumination of the area to be sensed by a light source (3) emitting shortwave light, especially in the green spectral area, and reception of reflected light by a photoreceptor (4).

Abstract: A new apparatus for treating substrates with fluids, as well as a corresponding fluid treatment method, is disclosed. The new apparatus includes a new configuration of fluid jet injectors which substantially overcomes the problem of dragout, in which fluid impinged upon an area of a substrate is retained on that area, preventing fresh fluid from reaching the impinged area. This new configuration also avoids imposing torques on substrates, and substantially reduces the need for rollers and guides for transporting substrates.

Abstract: The invention involves a TAB (tape automated bonding) tape which includes an electrically conductive layer and a supporting layer. Significantly, the supporting layer includes at least one peeling-prevention slit adjacent a part of the electrically conductive layer which is apt to peel off from the supporting layer when the TAB tape is subjected to stresses, such as thermally-induced stresses and bending stresses.

Abstract: A method for vapor phase depositing a thin seed layer of, for example, chromium and copper onto the side walls of through holes in thin film substrates of, for example, polyimide is disclosed. This method is useful in fabricating devices such as a thin film semiconductor chip carrier in which a semiconductor chip mounted on one major surface of the chip carrier is electrically connected to a ground plane and/or a power conductor on the other major surface of the chip carrier via one or more metallized through holes.

Abstract: A ceramic chip carrier is disclosed which preferably includes a ceramic substrate having a circuitized surface, at least one semiconductor chip mounted on the circuitized surface, and at least one pin which is mechanically and electrically connected to a contact pad on the circuitized surface. Each mechanical/electrical connection between a pin and a contact pad includes a conventional solder connection. In addition, each such solder connection is at least partially encapsulated in a material, including an epoxy resin, which is chosen in relation to the solder connection to enable the solder connection to withstand a standard thermal fatigue test.

Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.

Abstract: A circuit package is disclosed including a flexible printed circuit (10) which overlies, and follows the contour of, a carrier (50) having a substantially zig-zag shaped surface. The flexible printed circuit of this circuit package is in the form of a tape having a periodic, modular wiring pattern extending along the length of the tape, with connection lands provided between adjacent wiring modules. The circuit package also includes a plug for maintaining the flexible printed circuit in place on the carrier. Circuit components (20) mounted on the flexible printed circuit abut planar portions of the zig-zag shaped surface of the carrier (50).

Abstract: An apparatus for massive computation in integrated circuits provides the ability to calculate multiple dot products between an image focused on the integrated circuit surface and many reference patterns built into the integrated circuit, and then give an output indication for all those reference patterns where the dot product exceeds a threshold. The implementation, using current mirrors for multiplication with fixed constants, permits the integrated circuit to achieve large amounts of computation per unit area. This apparatus permits a large input data bandwidth, and by virtue of having enough computation capacity to complete a processing task on one chip, the output bandwidth is greatly reduced as well. The apparatus is employed, as an example, in a neural network. A set of connections between nodes that modify the value of the signal passed from one node to the next.

Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.