Patents Represented by Attorney, Agent or Law Firm Betty Formby
  • Patent number: 5805868
    Abstract: A graphics subsystem in which a very fast clear operation is performed without the need to address each pixel, and without using memories which include a hardware fast-clear capability. This is implemented by using a reference frame counter: the window is divided up into n regions, where n is the range of the frame counter (i.e. n=2.sup.p, where p is the number of bits in the frame counter). Every time the application issues a clear command, the reference frame counter is incremented (and allowed to roll over if it exceeds its maximum value), and only the n.sup.th region is cleared. The clear updates the depth and/or stencil buffers to the new values and the frame count buffer with the reference value. This region is much smaller than the full region the application thinks it is clearing, so takes less time and hence gives the speed increase. When the local buffer is subsequently read and the frame count is found to be the same as the reference frame count, the local buffer data is used directly.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: September 8, 1998
    Assignee: 3Dlabs Inc. Ltd.
    Inventor: Nicholas Murphy
  • Patent number: 5798770
    Abstract: The preferred embodiment discloses a pipelined graphics processor in which the sequence can be dynamically reconfigured (e.g. between primitives) in a rendering sequence. The pipeline sequence can be configured for compliance with specifications such as OpenGL, but may also be optimized by reconfiguring the pipeline sequence to eliminate unnecessary processing. In a preferred embodiment, pixel elimination sequences such as depth and stencil tests are performed before texturing calculations are performed, so that unneeded pixel data is discarded before said texturing calculations are performed.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: August 25, 1998
    Assignee: 3DLabs Inc. Ltd.
    Inventor: David Robert Baldwin
  • Patent number: 5789957
    Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: August 4, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Giona Fucili, Lorenzo Papillo, Andrea Pasquino, Annamaria Rossi, Alberto Gola
  • Patent number: 5786687
    Abstract: In a computer having switch-mode power converter, a pulse transformer circuit drives the converter's transistor switch in response to pulses from a switch control pulse source. A primary capacitor is connected in series with the switch control pulse source and the transformer's primary winding. At the leading edge of a switch control pulse, the primary capacitor causes a positive voltage spike to appear across the primary winding and hence a positive voltage spike to be induced across the transformer's secondary winding. At the trailing edge of the switch control pulse, the primary capacitor causes a negative voltage spike to appear across the primary winding and hence a negative voltage spike to be induced across the transformer's secondary winding.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: July 28, 1998
    Assignee: Compaq Computer Corporation
    Inventor: Richard A. Faulk
  • Patent number: 5781474
    Abstract: A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines of the matrix and supplied during the programming stage with a drain voltage which is boosted with respect to a supply voltage (Vcc). During the parallel programming stage the supply voltage is used as a drain voltage. Switching is provided between the supply using the drain voltage or the supply voltage during the transient between single word programming and parallel programming.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: July 14, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Mauro Sali, Fabio Tassan Caser, Stefan Schippers
  • Patent number: 5777629
    Abstract: A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: July 7, 1998
    Assignee: 3dLabs Inc. Ltd.
    Inventor: David Robert Baldwin
  • Patent number: 5774133
    Abstract: A computer system having a pixel processing unit with multiple subprocessors receives positional data defining graphical objects from the CPU and writes pixel data into the image memory, and a display driver produces an image which partially includes the rendered pixels. The pixel processor is used to access patches of multiple contiguous pixels at a time, and process them in parallel. The patches used are defined, within the overall geometry of the image, to have aligned corners. The unit is also connected to receive synchronization signals from the display driver, conditioned on whether the current line being accessed by the driver is within a specified range of lines in the image space.
    Type: Grant
    Filed: July 7, 1993
    Date of Patent: June 30, 1998
    Assignee: 3Dlabs Ltd.
    Inventors: John Walter Neave, Neil F. Trevett, Jonathan David Salkild, deceased, David Joseph Salkild, heir, Iain Stuart MacNaughton
  • Patent number: 5768118
    Abstract: A power converter which transfers energy from an output circuit coupled to a secondary winding of a power transformer to an input circuit coupled to a primary winding of the power transformer in order to reduce the power loss and electromagnetic interference (EMI) originating from a primary switch. The reciprocating action of the converter is accomplished by placing the series switched path of a secondary switch in parallel with a diode in the output circuit. A control circuit is coupled to the primary switch and the secondary switch which allows the inherent capacitance of each switch to discharge before turning on the respective switch, thereby reducing the EMI and power losses occurring at these switches. The control circuit includes feedback and feedforward voltage control of the switching duty cycle. The control circuit varies the energy transferred from the output circuit to the input circuit according to changes in the accumulated charge on the primary switch.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: June 16, 1998
    Assignee: Compaq Computer Corporation
    Inventors: Richard A. Faulk, J. Howard Ho
  • Patent number: 5766985
    Abstract: A process for making a package for discrete semiconductor devices, wherein the insulating characteristics of the package are increased by introducing cuts, grooves and positioning holes in the metal plate and shaping in the retractable positioning pins of the metal plate in the molding die.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: June 16, 1998
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Marcantonio Mangiagli, Rosario Pogliese
  • Patent number: 5764495
    Abstract: A variable-input-voltage variable-switching-frequency power converter with a minimum frequency limit. The switching frequency never goes below a certain minimum while the converter is on. Thus switching frequency is dependent on input voltage, for input voltages in one range, and is NOT dependent on input voltage, for input voltages in another range.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: June 9, 1998
    Assignee: Compaq Computer Corporation
    Inventor: Richard A. Faulk
  • Patent number: 5764228
    Abstract: A 3D graphics system in which a pre-rendering stage is combined with a rendering stage. Any GUI window which is not completely displayed on-screen (because it extends past screen boundaries or is overlapped by other windows, etc.), is divided into at least two portions, e.g. rectangles, for scissoring operations. If a primitive appears at least partially in some rectangle, rendering setup data is calculated, then applied against each rectangle in which it appears for a scissoring operation, and the portion of the primitive in that rectangle which survives the scissor is then rendered. The rendering data is stored between each scissoring function, and is not recalculated. Any portion of the primitive which does not appear in a rectangle is not rendered, thereby eliminating any rendering overhead for any primitive which would be completely hidden anyway.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: June 9, 1998
    Assignee: 3dLabs Inc., Ltd.
    Inventor: David Robert Baldwin
  • Patent number: 5764570
    Abstract: A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a reading cycle a single NOR gate, the output of which is provided with anti-overshoot means, enables the performance of a reading cycle. An input of the differential stage, is connectable to a common sensing line to which all the cells of the register are coupled in an OR configuration, while the other input is connectable to a reference current generator.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: June 9, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventor: Luigi Pascucci
  • Patent number: 5764243
    Abstract: A rendering system with multi-pixel span processing capability. When 3D graphics processes are not required, 2D data is processed in multi-pixel span fragments. Span fragments permit parallel processing of multiple pixels in a serial architecture, and permit VRAM block fills for accelerated processing under optimal conditions.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: June 9, 1998
    Assignee: 3DLabs Inc. Ltd.
    Inventor: David Robert Baldwin
  • Patent number: 5761322
    Abstract: A portable computer system including sealed acoustic suspension speaker enclosures which are each molded of a high density-low-density polymer combination, so that the low-density polymer can provide good sealing to adjacent surfaces. Preferably, neither speaker enclosure is sealed as a free standing unit, but the acoustic seal is completed only when the speaker enclosure is in place inside the portable computer.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: June 2, 1998
    Assignee: Compaq Computer Corporation
    Inventors: Patrick V. Illingworth, David E. Gough
  • Patent number: 5761222
    Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (A1) and being of the type comprising first memory, circuit (DM) designed to be accessed by means of address for containing user data, second memory circuit (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (A1) and the data input (DI) a writing address and user data respectively and to generate error data and to write, the data in the first circuit (DM) and second circuit (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to the data output (DO) and characterized in that the second, circuit (EM) is the type designed to be accessed by means of content and, the c
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: June 2, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventor: Livio Baldi
  • Patent number: 5751940
    Abstract: Integrated circuits can have both a microprocessor and an internal read-only memory of programs on one and the same chip. To facilitate the perfecting and finalizing of the programs of the read-only memory without undertaking the manufacture, for the perfecting and finalizing operation, of a special version of the circuit that is far too different from the definitive version, an external memory is used for the perfecting and finalizing operation. A contact pad of the chip is used for the transmission, in series mode, of a program coming from an external memory. A mode selection pad makes it possible to define whether the microprocessor must work in internal ROM mode (the normal mode) or in external ROM mode (the mode for the perfecting and finalizing operation).
    Type: Grant
    Filed: January 3, 1991
    Date of Patent: May 12, 1998
    Assignee: SGS Thomson Microelectronics, S.A.
    Inventor: Jean Nicolai
  • Patent number: 5748128
    Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: May 5, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Melchiorre Bruccoleri, Marco Demicheli, Giuseppe Patti, Valerio Pisati
  • Patent number: 5748002
    Abstract: Systems, methods, and probe devices for electronic monitoring and characterization using single-ended coupling of a load-pulled oscillator to a system under test.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: May 5, 1998
    Assignee: Phase Dynamics Inc.
    Inventors: Bentley N. Scott, Samuel R. Shortes
  • Patent number: 5745002
    Abstract: A switched capacitance circuit, using a switched operational amplifier structure as an input switch of the switched capacitance, is provided with a new biasing circuit. An additional switched capacitor, switched alternately to power supply and to ground, is connected to the output side of the primary switched capacitor. Precision is retained while ensuring a rail-to-rail dynamic range, without requiring boosted control phases. Special arrangements may be implemented for controlling the amplitude of switching spikes when so required. A fully differential embodiment is also feasible with additional advantages.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: April 28, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Andrea Baschirotto, Rinaldo Castello, Federico Montecchi, Angelo Nagari
  • Patent number: 5742796
    Abstract: A graphics subsystem which permits single buffered windows to exist in a double buffered system. Thus ALL the pixels on the screen are ultimately double buffered, but the single buffered should not appear to be double buffered. To support the single buffered windows, certain write operations are modified to write the same half-word of data into both the front and back half-words of an addressed location. This permits non-double buffered windows to remain correct when the RAMDAC.TM. is manipulated to swap buffers.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: April 21, 1998
    Assignee: 3Dlabs Inc. Ltd.
    Inventor: Philip Huxley