Patents Represented by Attorney, Agent or Law Firm Betty Formby
  • Patent number: 5742534
    Abstract: An electronic computation circuit comprises a multiplication operator with a serial input, a parallel input and a serial output, a first register connected by its output to the parallel input of the operator, a second register connected by its output to the serial input of the operator, a third register and a multiplexing circuit to selectively connect at least one data input terminal and the output of the operator to the inputs of the first, second and third registers, and to produce the output of the electronic multiplication circuit. Application to the operations of multiplication, squaring, exponentiation and modular inversion on a finite field denoted GF(2.sup.n).
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: April 21, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Guy Monier
  • Patent number: 5742546
    Abstract: In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder during a determined duration. The filtering signal is applied more particularly to the row decoder which selects a row corresponding to an address applied to the input of the decoder and applies a control voltage to this row. This method is particularly advantageous in low-voltage memories.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: April 21, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Jean Devin
  • Patent number: 5742548
    Abstract: In order to make it possible to ascertain that the programming cycles in an EEPROM type memory have been carried out efficiently, supplementary test cells are provided. A data writing operation is carried out in three successive cycles that consist in the programming of a test cell with a first logic value, a second cycle for the programming of the data elements and a third cycle for the programming of the test cell with a logic value that is complementary to the first one. The state of the test cell enables the detection of power interruptions during programming.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: April 21, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Yvon Bahout, Fran.cedilla.ois Tailliet
  • Patent number: 5740095
    Abstract: A multiplication circuit having a Booth decoder, a partial product generator and a computation and formatting circuit. An incrementing device is combined with the computation circuit, enabling an anticipated incrementation if it is desired to obtain a rounded result.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: April 14, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Philippe Parant
  • Patent number: 5740050
    Abstract: A parking citation issuing and enforcement system including an electronic citation writing device and an electronic parking meter. The system includes means whereby data, such as the status of the meter, may be transmitted between the electronic citation writing device and the electronic parking meter. The system also includes the ability to download the data from the electronic citation writing device to a computer for reporting of the citation data as well as the data retrieved from the electronic parking meter. This data cannot be manipulated while in the meter, during transmission to the electronic citation writing device, or during and after uploading to computer. Therefore, the report generated can be used in court to help resolve parking violation disputes.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: April 14, 1998
    Assignee: POM Incorporated
    Inventor: Seth Ward, II
  • Patent number: 5736876
    Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: April 7, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Richard Pierre Fournel
  • Patent number: 5734375
    Abstract: A method of determining an object's position and associated apparatus provides positional information in a form that may be conveniently communicated to a computer to calculate the object's position. In a preferred embodiment, representatively incorporated in a computer keyboard, a method of determining an object's position includes forming an optical grid of reflected beacons and detecting an obstruction of the reflected beacons. The preferred embodiment apparatus utilizes a single light source and a single light sensor to detect an object's position in two dimensions.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 31, 1998
    Assignee: Compaq Computer Corporation
    Inventors: Richard M. Knox, John R. Masters, Kevin F. Clancy
  • Patent number: 5734287
    Abstract: Distortion control in a push-pull output stage of a speech amplifier of a telephone powered through the telephone line is more effectively and advantageously implemented by independently sensing an eventual state of saturation reached by any of the two output transistors of the amplifier, summing the current signals representative of the sensed state of saturation of either or both output transistors, integrating the resulting sum current signal to produce a DC signal and using the DC signal for activating an AGC loop. The DC signal indiscriminately accounts for any cause of saturation, though virtually representing the level of the amplified AC signal. Distortion may be controlled without penalizing output voltage swing and power consumption.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: March 31, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Pietro Consiglio, Carlo Antonini
  • Patent number: 5732012
    Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: March 24, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Paolo Cappelletti, Silvia Lucherini, Bruno Vajana
  • Patent number: 5731716
    Abstract: A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: March 24, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventor: Luigi Pascucci
  • Patent number: 5726604
    Abstract: The dynamic range of operation of a differential transconductance input stage is reduced when the amplitude of the input signal decreases, thus reducing the level of the noise that is generated by the input stage. A DC signal representative of the sensed amplitude of the input signal is employed for either reducing the value of a common, emitter-degenerating resistance or of the bias current that is forced in the two branches of the differential input stage.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: March 10, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Andrea Mario Onetti, Domenico Rossi
  • Patent number: 5727192
    Abstract: A device and method for providing a frame buffer interface to a serial rendering system which automatically synchronizes with data in the rendering path before blanking the active frame. To prevent rewriting to a frame buffer of rendered data before the current rendered data can be displayed, the disclosed embodiment provides that when the data is ready to be displayed, all further writes to the buffer are suspended, while all other accesses throughout the system are allowed to proceed. When the vblank command is received, data is passed to the display system for display, and writes to that buffer are re-enabled. When writes to a specific buffer portion are suspended, all other processes may continue independently.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: March 10, 1998
    Assignee: 3DLabs Inc. Ltd.
    Inventor: David Robert Baldwin
  • Patent number: 5727169
    Abstract: The use of electromechanical devices for the configuration of the address for access to a peripheral unit in a data-processing system is avoided by replacing them with a non-volatile EEPROM-type memory. The data in non-volatile memory is read as soon as the peripheral unit is put into operation, and the information that it delivers is stored in volatile memory and used as a comparison address to validate the operation of the peripheral unit.
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: March 10, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Philippe Calzi
  • Patent number: 5723350
    Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: March 3, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Gabriella Fontana, Orio Bellezza, Giuseppe Paolo Crisenza
  • Patent number: 5715204
    Abstract: The differential input stage of a sense amplifier is provided with a positive feedback for introducing a predefinable hysteresis that will prevent spurious transitions of the output of the sense amplifier, enhancing noise immunity. The positive feedback is realized by employing an inverting amplifying stage, which will introduce an hysteresis on one of the two switching phases. The thresholds of the sense amplifier may be made symmetric by modifying the area ratio of the load transistors.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: February 3, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventor: Antonio Barcella
  • Patent number: 5714899
    Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: February 3, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Sylvie Wuidart, Tien-Dung Do
  • Patent number: 5710729
    Abstract: An oversampling digital filter with Finite Impulse Response is implemented using a serial structure having a memory for the coefficients, a memory for the signal samples to be filter, a multiplier connected to the output of the memories, an accumulator connected to the output of the multiplier, and a simple control unit which controls these elements according to an input clock signal.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: January 20, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Sandro Delle Feste, Marco Bianchesi, Alessandro Cremonesi
  • Patent number: 5710934
    Abstract: Methods and test platforms for developing an application-specific integrated circuit incorporating, on the same chip, a signal processor core, RAM memory and ROM memory intended to receive a management program and processing program, and input-output management peripherals specific to the application. The signal processor, RAM memory and ROM memory correspond respectively to existing separate IC components. The processing program is developed and tested on a test platform including at least these separate IC components together with a core-emulation integrated circuit, which includes the signal processor core in a minimal configuration. An interface program and diagnostic interface logic allows the platform to be controlled from a microcomputer, which can thereby implement automatic chaining of tests.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: January 20, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Mariano Bona, Pierre-Albert Comte, Duc Pham-Minh
  • Patent number: 5710739
    Abstract: A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 20, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Cristiano Calligaro, Roberto Gastaldi, Paolo Rolandi, Guido Torelli
  • Patent number: 5710811
    Abstract: The speech circuit matches the impedance of the telephone line by synthesizing a complex impedance using a positive feedback loop which has a single resistor (11), and cancels out the side tone using a subtractor (20') which extracts from the signal (Va) coming from the line a signal (Vb) correlated to the signal to be transmitted. In order to achieve cancellation of the side tone unaffected by the noise produced in the impedance synthesizing circuits, the signal (Vb) is derived by processing the signal present in the resistor (11) at the output of the feedback loop.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: January 20, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Luciano Tomasini, Rinaldo Castello, Ivan Bietti, Giancarlo Clerici