Patents Represented by Attorney, Agent or Law Firm Bever, Hoffman & Harms, LLP
  • Patent number: 8351492
    Abstract: Embodiments of the present invention provide an apparatus comprising a transceiver having a receiver and a transmitter connected through a segment of a calibration loop back path. The apparatus also comprises a control system configured to communicate with the transceiver. The calibration loop back path has an intentional phase shift that can be toggled between an off state and an on state by the control system. The control system is configured to calculate the intentional phase shift by examining the difference of a first and second phase angle. The first phase angle is obtained from the transmission of a first pair of signals with the intentional phase shift in the off state. The second phase angle is obtained from the transmission of a second pair of signals with the intentional phase shift in the on state.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 8, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Yann Ly-Gagnon
  • Patent number: 8349668
    Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 8, 2013
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Tsu-Jae King Liu
  • Patent number: 8346288
    Abstract: Transient distortion is compensated for by multiplying an exponentially-decaying phase shift onto the distorted waveform. The exponentially decaying phase shift waveform is patterned after the transient which typically takes the form of an exponential and occurs upon introduction of power to a circuit or circuit component. A digital circuit produces an appropriate exponentially-decaying waveform which is used as the input for a look up table whose output is a complex sinusoidal waveform capable of compensating for the distortion. The complex sinusoid is multiplied onto the transmitted waveform. The decaying exponential is biased so that it crosses a threshold at which point the compensating circuitry is turned off.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: January 1, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Paul J. Husted, Bevan M. Baas
  • Patent number: 8341812
    Abstract: A cremated remains memorial container including a box defining an upper box opening, a picture frame panel attached to the box such that a picture slot is defined between the picture frame panel, and a cover panel that is disposed in the picture slot and has an indented portion extending into the upper box opening. The cover panel is formed from an opaque material, and is slid into the picture slot after the cremated remains are inserted into the box, thereby obscuring the remains. A picture is then inserted in the remaining (residual) space between the cover panel and the picture frame through the picture slot opening. The indented portion of the cover panel engages with the inner edge of the upper box opening, whereby subsequent removal of the cover panel from the picture slot is resisted during removal/replacement of the picture.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: January 1, 2013
    Inventor: Marc L. Kocir
  • Patent number: 8344440
    Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: January 1, 2013
    Assignee: Tower Semiconductor Ltd.
    Inventors: Evgeny Pikhay, Micha Gutman, Yakov Roizin
  • Patent number: 8344468
    Abstract: A photovoltaic device includes lateral P-I-N light-sensitive diodes respectively formed in portions of a planar semiconductor material (e.g., polycrystalline or crystalline silicon) layer that is entirely disposed on an insulating material (e.g., SiO2) layer utilizing, e.g., STI or SOI techniques. Each light-sensitive diode includes parallel elongated doped regions respectively formed by P+ and N+ dopant extending entirely through the semiconductor layer material and separated by an intervening elongated intrinsic (native) region. The light-sensitive diodes are connected in series by patterned conductive (e.g., metal film) structures. Optional bypass diodes are formed next to each lateral P-I-N light-sensitive diodes. Optional trenches are defined between adjacent light-sensitive diodes.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: January 1, 2013
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay
  • Patent number: 8340598
    Abstract: A dual mode power amplifier can include a linear gain section and a non-linear gain section configured together as a polar amplifier. The dual mode power amplifier may be used to transmit GFSK, 4-DPSK, and 8-DPSK modulated data. In one mode, both non-linear and linear gain sections may be used to transmit 4-DPSK and 8-DPSK modulated data. Alternatively, in another mode, the linear gain section may be bypassed while the non-linear gain section may be used to transmit GFSK modulated data. By selecting the operating mode, the dual mode power amplifier may be advantageously configured to use relatively less power while supporting GFSK, 4-DPSK, and 8-DPSK modulation schemes.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: December 25, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: MeeLan Lee, William W. Si, David J. Weber
  • Patent number: 8335536
    Abstract: Wireless devices may contain multiple radio transceivers, each conforming to different communication protocols. A first transceiver conforming to a first communication protocol in a first wireless device may be able to receive, detect, and/or decode messages transmitted by a second transceiver in a second wireless device conforming to a second communication protocol. The first transceiver may communicate received, detected, and/or decoded information to a different transceiver in the same first wireless device, thus enabling the collocated transceivers to work in concert efficiently. A wideband transceiver using a set of multiple sub-channels in parallel may receive, detect, and/or decode messages transmitted by a narrowband transceiver using a set of multiple channels serially, thereby reducing scan time and power consumption.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 18, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Olaf Hirsch, Paul J. Husted
  • Patent number: 8336015
    Abstract: A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: December 18, 2012
    Assignee: Synopsys, Inc.
    Inventors: Changge Qiao, Chi-Min Chu, Jing C. Lin
  • Patent number: 8335284
    Abstract: An apparatus and method in a multiple sub-carrier digital communication receiver for reducing inter-channel interference (ICI) includes a channel estimation block for calculating channel estimates, an interpolation block for calculating interpolated channel estimates, and an ICI reduction block for calculating ICI reduced receive symbols. Channel estimates are calculated based on receive symbols or ICI reduced receive symbols using pre-determined transmit symbols. Interpolated channel estimates are calculated by Wiener filter interpolation of a set of channel estimates. ICI estimates are calculated based on a set of interpolated channel estimates and either receive symbols or ICI reduced receive symbols. ICI reduced receive symbols are generated by subtracting ICI estimates from receive symbols.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: December 18, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Gaspar Lee, Hao-Ren Cheng, Chih-Yuan Chu, Kuang-Chung Ou
  • Patent number: 8335884
    Abstract: A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: December 18, 2012
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Mehrdad Hamadani, Deepak Bansal, Sam Htin Moy, Sreenivasulu Malli, David Cheung, Mani Kancherla, Sridhar Devarapalli
  • Patent number: 8330485
    Abstract: A curved spring structure includes a base (anchor) section extending parallel to a planar substrate surface, a cantilever section extending away from the substrate surface, and an optional elongated section extending from the base section along the substrate surface under the cantilevered section. The cantilever section includes a body portion integrally attached at a lower end to the anchor section and extending at an acute angle relative to the planar surface, and a curved portion integrally attached to an upper end of the body portion and including a downturned tip. A middle section of the curved portion is disposed a first distance away from the planar surface of the substrate, and the downturned tip is disposed a second distance away from the planar surface of the substrate, the first distance being greater than the second distance.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 11, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene M. Chow, Dirk DeBruyker
  • Patent number: 8331462
    Abstract: A method and apparatus to selectively disregard co-channel transmissions on a medium uses an automatic gain control/clear channel assessment (AGC/CCA) circuit to gather signal power information, which is used to establish receiver sensitivity thresholds. Raw and cyclical power measurements of a received signal are processed by the AGC/CCA circuit to determine whether a current received signal process should be halted, and a new signal acquisition sequence begun.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: December 11, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Paul J. Husted, William J. McFarland
  • Patent number: 8325689
    Abstract: To efficiently transmit data on a wireless network, small packets that might otherwise be sent individually are aggregated into a “superframe”. This superframe can then be transmitted as a single, larger packet. To form this superframe, a plurality of tagged data packets can be aggregated into a packed aggregation block (PAB). Encapsulation data, e.g. protocol information, can be appended to the PAB. Wireless transmission information can bound the PAB and encapsulation data. Forming the superframe can be performed using an efficient combination of hardware and software. In one embodiment, aggregation of the tagged data packets can be performed by hardware without regard to the underlying protocol(s). Software can then provide protocol-handling support.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: December 4, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventor: Jeffrey S. Kuskin
  • Patent number: 8295404
    Abstract: One embodiment of a DPSK receiver includes an ADC, a down-sampler, and a timing tracker. The ADC samples a received DPSK signal providing sub-samples of a digital signal. The timing tracker examines differences between amplitudes of currently selected sub-samples and sub-samples before and after the currently selected sub-samples. The differences may indicate a timing adjustment may be made to the digital signal. The timing tracker may change the timing of the digital signal by modifying the configuration of the down-sampler. Additionally, the timing tracker may also correct phase errors introduced by configuration changes of the down-sampler.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: October 23, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Paul J. Husted, Soner Ozgur
  • Patent number: 8295263
    Abstract: A process for determining when sounding packets are to be triggered and transmitted in a wireless beamforming system is disclosed. In one embodiment, a timer is programmably set to adapt to the operating environment. Whenever the timer elapses, a sounding packet is triggered and the timer resets. In another embodiment, the sounding packet is triggered by comparing measured correlations of channel characteristics against a programmable correlation threshold. If a measured correlation falls below the correlation threshold, this indicates that the channel has undergone a relatively large change. In response, a new sounding packet is triggered to update the beam steering matrix. Otherwise, the previous beam steering matrix is still used. Thereby, sounding packets are expeditiously triggered to keep the beam steering matrix updated with minimal impact to the over-the-air bandwidth.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: October 23, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Chin Hung Chen, Ning Zhang
  • Patent number: 8287744
    Abstract: Fluidic conduits, which can be used in microarraying systems, dip pen nanolithography systems, fluidic circuits, and microfluidic systems, are disclosed that use channel spring probes that include at least one capillary channel. Formed from spring beams (e.g., stressy metal beams) that curve away from the substrate when released, channels can either be integrated into the spring beams or formed on the spring beams. Capillary forces produced by the narrow channels allow liquid to be gathered, held, and dispensed by the channel spring probes. Because the channel spring beams can be produced using conventional semiconductor processes, significant design flexibility and cost efficiencies can be achieved.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 16, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Thomas Hantschel, David K. Fork, Eugene M. Chow, Dirk De Bruyker, Michel A. Rosa
  • Patent number: 8289086
    Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: October 16, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Shuo-Wei Chen, David Kuochieh Su
  • Patent number: 8286049
    Abstract: A configurable transmitter for a wireless communication system may include a flexible block coder, an IFFT block, an analog and RF block, and an antenna coupled in series. The flexible block coder may advantageously perform forward error correction and mapping of a data stream to generate a processed data vector. To perform these functions, the flexible block coder may include a data formatter and a multiplier. The data formatter may format the data stream into an output vector, whereas the multiplier may multiply the output vector by a configurable channel coding matrix to generate the processed data vector. The size of the output vector may be a reflection legacy compatibility and data rate. The size of the processed data vector is equal to a product of the output vector and an inverse of a coding rate. The channel coding matrix may be compressed.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 9, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: William J. McFarland, Kai Shi, Bruce Busby
  • Patent number: 8286048
    Abstract: A method for decoding an LDPC (low-density parity check) code word. The method includes receiving a plurality of LLR (log likelihood ratio) terms from a demodulation unit of a receiver and generating a scaling factor in accordance with at least one parameter descriptive of communication channel conditions for the receiver. The scaling factor is applied to each of the plurality of LLR terms to compute a corresponding plurality of scaled LLR terms. An iterative layered belief propagation algorithm is then executed by using the plurality of scaled LLR terms to generate decoded information.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 9, 2012
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Qifan Chen, Ning Zhang