Abstract: A polar transmitter includes a phase monitoring unit for monitoring input modulating data. When a phase transition exceeds a phase transition threshold, the phase monitor unit can signal an amplitude negation unit to invert the amplitude data coupled to the polar amplifier. The phase monitoring unit can also add an offset to the phase data that is provided to a frequency synthesizer. In another embodiment, when the phase transition threshold is exceeded, the phase monitoring unit can trigger inverting differential frequency data coupled to the polar amplifier. In one embodiment, the phase offset and the amplitude negation are applied until a second phase transition value exceeding the phase transition threshold is detected. If such an event is detected, then the input amplitude data is no longer inverted and the phase offset value is no longer added to the modulating data.

Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.

Abstract: A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer with a frequency to convert a signal to a higher intermediate (IF) frequency. The output of the mixer is fed to a poly-phase filter. The output of the poly-phase filter is fed to a programmable gain amplifier (PGA), whose output is fed to an analog-to-digital converter (ADC) to produce an output GPS signal. A saturation bit of the ADC is used to control the PGA through a digital amplifier gain control (AGC) circuit.

Abstract: Simulating hardware includes generating a data flow representation of the hardware, based on a hardware description language (HDL) description. The data flow representation including compatibility information that preserves behavioral and synthesizable characteristics of the HDL description. Simulating hardware further includes generating code from the data flow representation, and executing the code concurrently.

Abstract: A method of performing formal verification on a design for an integrated circuit can include accessing a set of constraints for the design. These constraints can be partitioned based on their variables, wherein any overlapping variables can result in the conjoining of their corresponding constraints. Binary decision diagrams (BDDs) can be generated based on such conjoining. Notably, invariants can be derived from the BDDs. These invariants can include constant, symmetric/implication, one-hot/zero-hot, and ternary invariants. Deriving the invariants can include cofactoring and counting of minterms of the BDDs. Using the invariants while performing formal verification on the design can advantageously optimize system performance.

Abstract: A set of global location signals, an SBAS (Satellite Based Augmentation System), or an ACI (ambient country identifier) signal can be used to automatically provide location awareness for a WLAN device. If one of the set of global location signals, the SBAS signal, or the ACI signal is detected, then the WLAN device can configure itself to comply with channel and power settings for the country/region having the detected signal(s). After configuration, the WLAN device can be “locked” to the country/region having the signal(s), thereby ensuring legal operation of the WLAN device even after subsequent restarts. If one of the signals is not detected, then the WLAN device can be configured in a default mode, e.g. an “open mode” in which end users can configure the WLAN device by entering a country of operation or a “common mode” in which the channel and transmit power settings meet global spectrum usage requirements.

Abstract: A system and method for synchronously transmitting media data is described. Synchronization data may be transmitted by a cycle master for receipt by one or more cycle slaves. A cycle slave may update an internal state based on the synchronization data received from the cycle master. The cycle master may transmit media data to multiple cycle slaves. The media data output by the cycle slaves may be determined, in part, by the internal state. In one embodiment, the media data may determine which cycle slave receives particular media data.

Abstract: A method and apparatus in a multiple sub-carrier digital communication receiver estimates a Doppler frequency bandwidth. The Doppler frequency bandwidth is estimated by comparing a first set of channel estimates to a second set of channel estimates generated by Wiener filter interpolation of the first set of channel estimates. The Wiener interpolation filter coefficients are generated for various Doppler frequency bandwidths. Pre-determined transmit pilot symbols may be used to generate the first set of channel estimates in an OFDM communication system. A set of Wiener filter interpolation errors may be generated at one or more sub-carrier frequencies, for each of the different Doppler frequency bandwidths, and averaged across time and/or frequency. The Doppler frequency estimation method and apparatus may select a Doppler frequency estimate based on the set of Wiener filter interpolation errors.

Abstract: A relaxed InGaN template employs a GaN or InGaN nucleation layer grown at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention.

Abstract: An apparatus for processing a Bluetooth signal advantageously mixes down a received RF signal to an IF signal wherein one band-edge of the spectrum of the IF signal may be approximately 0 Hz. In one embodiment, the IF signal may be digitized, decimated and filtered before being processed into a baseband signal. The baseband signal may be processed by a cordic (COordinate Rotation DIgital Computer) processor to transform the baseband signal from rectangular to polar coordinates. A phase signal from the cordic processor may be used to determine transmitted Bluetooth data symbols. The apparatus may advantageously use less area than traditional Bluetooth receivers.

Abstract: A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCBs arranged in parallel rows, with each PCB connected to its neighboring PCBs in each row by relatively narrow connecting bridge pieces, and separated from PCBs of adjacent rows by elongated stamped out blank slots. Passive components are attached by conventional surface mount technology (SMT) techniques. IC chips, including a MicroSD controller chip and a flash memory chip, are attached to the PCB by wire bonding or other chip-on-board (COB) technique. A molded housing is then formed over the IC chips and passive components using a mold that prevents formation of plastic on the upper surface of each PCB. The connecting bridge pieces are then cut using using a rotary saw. A front edge chamfer process is then performed.

Abstract: Wireless devices may contain multiple radio transceivers, each conforming to different communication protocols. A first transceiver conforming to a first communication protocol in a first wireless device may be able to receive, detect, and/or decode messages transmitted by a second transceiver in a second wireless device conforming to a second communication protocol. The first transceiver may communicate received, detected, and/or decoded information to a different transceiver in the same first wireless device, thus enabling the collocated transceivers to work in concert efficiently. A wideband transceiver using a set of multiple sub-channels in parallel may receive, detect, and/or decode messages transmitted by a narrowband transceiver using a set of multiple channels serially, thereby reducing scan time and power consumption.

Abstract: A relaxed InGaN template is formed by growing a GaN or InGaN nucleation layer at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures on the nucleation layer. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention.

Abstract: After detecting the predetermined phase rotation, a receiver can advantageously remove any cyclic shifting delays (CSDs) from the mixed mode packet for each chain. Once any CSDs are removed, the receiver can perform timing offset estimation and decode the mixed mode packet. In another embodiment, a timing offset from a channel for a first chain without any CSDs can be estimated. Compensation for the timing offset in the first chain can then be performed. At this point, the CSDs from other chains can then be removed. After CSD removal, compensation for any timing offsets in the other chains can be performed using the timing offset in the first chain.

Abstract: A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.

Abstract: A switchable inductor-capacitor-inductor (L-C-L) network, which includes an integrated T/R switch, can advantageously bridge a PA and an LNA of a wireless device. The first inductor can function as an RF choke that provides power to the PA. In one embodiment, the first inductor can be advantageously implemented using the bond wires already attached to the PA, thereby requiring no additional inductors to provide the integrated T/R switch and minimizing use of valuable silicon area. The second inductor can function as a source inductor for and cancel an input parasitic capacitance of the LNA. A set of capacitors can act as blocking capacitors to provide DC isolation between the LNA and the PA, thereby protecting the LNA from high voltages. The L-C-L network can also advantageously function as an impedance matching network for at least one of the PA and the LNA.

Abstract: A method of texturing a surface within or immediately adjacent to a template layer of a LED is described. The method uses a texturing laser directed through a substrate to decompose and pit a semiconductor material at the surface to be textured. By texturing the surface, light trapping within the template layer is reduced. Furthermore, by patterning the arrangement of pits, metal coating each pit can be arranged to spread current through the template layer and thus through the n-doped region of a LED.

Abstract: In a multiple-input multiple-output communication system, a transmit symbol vector and a set of soft decision metrics may be estimated using a reduced complexity maximum likelihood (ML) detection method based on a receive symbol vector and a QR decomposition of a set of permuted channel matrices. The reduced complexity ML detection method may use a different permuted channel matrix to estimate each transmit symbol in a transmit symbol vector. A set of error distances may be calculated for the estimated transmit symbol vector, each error distance calculated choosing a different value from a signal constellation subset for a transmit symbol in the estimated transmit symbol vector. A soft decision metric may be calculated using the elements from the set of error distances. In some embodiments the transmit symbols of a transmit symbol vector and the soft decision metrics for each transmit symbol may be determined in parallel.

Abstract: A low drop out voltage regulator (LDO) is capable of operating in one of two different modes based on externally connected components. In one mode, the LDO directly generates a regulated output voltage. In a second mode, the LDO drives an external PNP transistor to generate a regulated output voltage. In both modes, a relatively large bypass capacitor may be connected to the output voltage node to bypass high-frequency loading on the output voltage node. However, the bypass capacitor creates a low frequency pole in the frequency response of the LDO, which can diminish phase margin and reduce overall stability. An on chip compensation network beneficially counteracts the low frequency pole with an appropriately placed zero, thereby resulting in improved phase margin and greater stability.