Abstract: Methods of operation of an active pixel sensor cell to provide electronic shuttering and elimination of image lag are disclosed. An active pixel sensor has a photodiode, a bipolar transistor, a pass MOS transistor, and a parasitic MOS transistor. The first method of operation of the active pixel sensor will vary the time the integration time of the active pixel sensor by adjusting the time of a resetting pulse to the anode of the photodiode to eliminate any accumulated charge relative to the integration time. The second method will place the anode of the photodiode in a sleep mode by resetting the anode of the photodiode for a period of time. The relative time of the sleep mode to the integration time will determine the electronic shuttering. The third method to eliminate the image-lag overlaps the read period and the sleep time, and brings the reset biasing voltage source to a lower level to extract all the minority carriers from the base of the bipolar transistor.

Abstract: A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator.

Abstract: A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.

Abstract: A multiple phase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate by first applying a first relatively large negative voltage pulse to the control gate. Concurrently a first moderately large positive voltage pulse is applied to the source. Also, concurrently a ground reference potential is applied to the first well and the semiconductor substrate, and the drain and second well are disconnected to allow the drain and second well to float.

Abstract: A pseudo random pulse generator that creates a series of pulses having randomly separated intervals is described. A pseudo random pulse generator has a pseudo random number generator create a series of pseudo random binary numbers. An enable input initiates creating the series of pseudo random binary numbers and a clock input is connected to a clock signal that synchronizes creating the series of pseudo random binary numbers. A hold input prevents the generation of the pseudo random binary numbers. The pseudo random pulse generator has an interval selector to select one of a plurality of timing signals. Each timing signal is a power of two frequency division of the clock. The interval selector has select signal terminals to select one of the plurality of timing signals, and a trigger output to hold a selected timing signal. The pseudo random pulse generator further has a select buffer connected to a low order digits of the pseudo random number generator.

Abstract: An acoustic signal processing subsystem for an electronic stereophonic audio system is disclosed. The acoustic signal processing subsystem will modify electronic audio signals such that sound broadcast from loudspeakers will be perceived as mimicking the quality of sound broadcast in an acoustically ideal room. The acoustic signal processing subsystem has a left signal processor coupled to a left acoustic signal source to modify the left acoustic signal and to couple a first modified left acoustic signal to a left speaker, and a right signal processor coupled to a right acoustic signal source to modify the right acoustic signal and to couple a first modified right acoustic signal to a right speaker.

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock.

Abstract: Systems and methods for the detection of motions of a pointed object upon a writing surface such as a touchpad is disclosed. The motions will be detected and converted in a multiplexing analog-to-digital converter to digital codes representing the location of the pointed object and the pressure of the pointed object upon the touchpad. The location and the pressure will be translated into a pen detect signal indicating the presence of the pointed object upon the touchpad. The pen detect signal will be translated into a stroke signal to interpret a single tap, a double tap, and a tap and drag of the pointed object on the touchpad. The digital codes will be averaged to minimize noise and formed into an absolute coordinates digital code. The absolute coordinate digital code, the pressure digital code, and the pen detect signal will be converted to a touchpad-computer interface protocol. Further, multiple sets absolute coordinates will translated into a relative motion code.

Abstract: A semiconductor wafer carrier fork cover to prevent damage to prevent breakage of the semiconductor wafer carrier forks mounted on a robotic semiconductor wafer transfer system during preventative maintenance procedures is described. A semiconductor wafer carrier fork cover has a lower support unit. The lower support unit will fit onto the base of a robotic semiconductor wafer transfer system. An upper covering unit is integrally attached to the lower support unit and will shield the semiconductor wafer carrier forks during preventive maintenance procedures.

Abstract: A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

Abstract: An active pixel sensor cell that will convert a quantum of light energy to an electronic signal representing the amplitude of the quantum of light energy is disclosed. The active pixel sensor cell is immune to image blooming and has a reset operation to reduce image lag. An active pixel sensor has a photodiode, a bipolar transistor and a MOS transistor. The photodiode has a cathode connected to a power supply voltage source and an anode to the MOS transistor. The quantum of light energy will impinge upon the anode and generate electric charges within the photodiode. The MOS transistor will prevent the image blooming by disconnecting the anode of the photodiode from the base of the bipolar transistor and connecting the anode of the photodiode to MOS transistor to allow the electric charges in the photodiode to flow through the MOS transistor. The bipolar transistor will amplify the electrical charges to create the electronic signal. The active pixel sensor further includes a parasitic MOS transistor.

Abstract: The present invention provides a voltage controlled oscillator with improved noise immunity and minimized variation due to manufacturing process, power supply and operating temperature changes. The voltage controlled oscillator consists of fully differential connected ring oscillator that includes a plurality of differentially connected delay elements. The ring oscillator responds to a control current signal for controlling the frequency of oscillation. A voltage to current converter converts the input tuning voltage to an output current for the controlling of the ring oscillator. The delay element consists of two source coupled P-channel transistors connected to a current source. The drains of the P-channel transistors are each connected to a voltage controlled impedance that changes the delay characteristics of the delay element in response to the input tuning voltage.