Abstract: One embodiment of a circuit and corresponding method for generating a trigger signal upon the occurrence of either set up or hold time violations in the same waveform acquisition produces a trigger signal referenced to, but displaced in time from, the input clock signal. Transitions (13) in a data signal initiate a window pulse (14') whose duration is equal to the sum of a set up time requirement and a hold time requirement. The window pulse is used as the D input to a flip-flop (20) that is clocked by a version of a clock signal whose active edge has been delayed (28) for an interval that corresponds to the hold time requirement. The output of the flip-flop (20) is a trigger signal that only occurs when a set up or hold time violation has occurred. In another embodiment, triggers generated as the result of a set up time violation are referenced to the clock edge, while triggers that are generated as the result of a hold time violation are referenced to a transition in the data signal.

Abstract: A first subset of components of a first set of pairs of complementary differential electrical signals representative of a numerical value expressed in a multi-bit thermometer code, is processed in accordance with a first set of Boolean functions to produce a first set of output electrical signal components , and a second subset of components of the first set of pairs of complementary differential electrical signals is processed in accordance with a second set of Boolean functions to produce a second set of output electrical signal components. The first and second subsets and the first and second sets of Boolean functions are such that the first and second sets of output electrical signal components when combined form a second set of pairs of complementary differential electrical signals representative of the same numerical value expressed in a second multi-bit code with fewer bits than the multi-bit thermometer code.

Abstract: Methods for producing logic signal displays for an instrument known as a "logic oscilloscope" are disclosed. A digital input signal is first sampled as an analog signal to produce multi-bit digital samples that are representative of the amplitude of the input signal over time. The multi-bit digital samples are then processed using interpolative techniques to ascertain when the input signal crossed a hypothetical logic level threshold or pair of thresholds and when the signal was in one logic state or the other. The resulting transition times and logic states are then used as the basis for generating a variety of digital displays, including logic timing diagrams, state table displays, and cursor readouts similar to those available in a logic analyzer. Setup and hold time violations and measurements may also be obtained using this information.

Abstract: A zero dead time acquisition system for a digital storage oscilloscope (DSO) has an input buffer that stores an initial value from an acquisition memory for each sample interval of an input analog signal. The input analog signal is oversampled and digitized so that there are multiple digitized samples of the analog signal for each sample interval. At the beginning of a sample interval the initial value from the input buffer is transferred to an accumulation register, the output of which is compared with the multiple samples of the analog signal during the sample interval. If any of the multiple samples falls outside the limit determined by the value in the accumulation register, in a save on delta mode a latch is set to generate an error signal that terminates further acquisition cycles. In an envelope mode the comparison result causes the value in the accumulation register to be replaced with the sample value that fell outside the limit to establish a new limit, either maximum or minimum.

Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: A method and circuit for conditioning a received analog signal for input to an analog-to-digital converter circuit ("ADC"). For each clock period in which a conversion is triggered, a first analog value is provided during a first predetermined period and a second analog value is provided during a second predetermined period. The first analog value is representative of the received analog signal's instantaneous value at the moment selected for conversion. The second analog value is predetermined, typically being a null value. The signal conditioning circuit includes a hold circuit to hold the received analog signal's instantaneous value; a generating circuit that generates the second analog value; and an output circuit that selectively outputs the instantaneous value or the predetermined value to the ADC.

Abstract: A fully differential comparator includes a differential signal input, a differential reference input, and a differential signal output. Identical first and second gain stages are used in the differential comparator that each have a first single-ended input, a second single-ended input, and a differential output. The first single-ended inputs from the first and second gain stages form the differential signal input of the differential comparator. The second single-ended inputs from the first and second gain stages form the differential reference input of the differential comparator. The differential outputs of the first and second gain stages are cross-coupled to form the differential signal output of the differential comparator. The differential comparator can be used in conjunction with a conventional resistor string found in the front end of a flash ADC, but in a novel manner that prevents undesirable loading effects, as well as other problems associated with prior art single-ended comparators.

Abstract: The invention is a method for accumulating and displaying digital waveform data, representing the behavior over time of an electrical signal that includes the steps of: repeatedly acquiring and digitizing (10) waveform data during a first set of time intervals, repeatedly acquiring and digitizing (10) waveform data during a second set of time intervals, the second set of time intervals alternating with the first set of time intervals, during each one of the time intervals in the first set of time intervals, ORing (83) each acquired and digitized waveform together to produce first composite waveforms, during each one of the time intervals in the second set of time intervals, ORing (86) each acquired and digitized waveform together to produce second composite waveforms, displaying (81,84) each first composite waveform during a next occurring time interval in the second set of time intervals, and displaying (81,84) each second composite waveform during a next occurring time interval in the first set of time inte

Abstract: Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.

Abstract: An improvement is provided for current sources of the type having three transistors configured as follows: The bases of the first (Q1) and second (Q2) transistors are tied together. The collector of the first transistor (Q1) is coupled to a first voltage (V.sub.CC,V.sub.EE) via a first resistor (R1). The emitter of the first transistor (Q1) is coupled to a second voltage (V.sub.EE,V.sub.CC) via a second resistor (R2). The collector of the second transistor (Q2) produces the output current (I.sub.OUT). The emitter of the second transistor (Q2) is coupled to the second voltage (V.sub.EE,V.sub.CC) via a third resistor (R3). The base of the third transistor (Q3) is coupled, either directly or indirectly through a fourth transistor (Q4), to the collector of the first transistor (Q1). The collector of the third transistor (Q3) is connected to the first voltage (V.sub.CC,V.sub.EE) and the emitter of that transistor (Q3) is connected to the bases of the first (Q1) and second (Q2) transistors.

Abstract: Apparatus for generating a phase startable clock signal, comprises an oscillator for providing a continuous sinusoidal input signal, a control signal source for providing a control input signal having a transition between a first state and a second state at a selected time during the signal epoch of the sinusoidal input signal, and a phase splitter, track and holds, multipliers and a summation device for operating on the sinusoidal input signal with the control input signal to produce a sinusoidal output signal commencing with a predetermined phase at a predetermined time relative to the transition.

Abstract: A transistor amplifier having a main amplifier exhibiting a substantially doubled f.sub.T characteristic and having error cancellation circuitry, wherein the standing current of the error cancellation circuitry is reused in powering the main amplifier. The main amplifier comprises an outer differential pair of transistors and an inner differential pair of transistors, each differential pair having an inverting side and a non-inverting side. The collectors of the transistors of the non-inverting side of the differential pairs are connected, respectively, at a first current summing node. The collectors of the transistors of the inverting side of the differential pairs are connected, respectively, at a second current summing node. The f.sub.

Abstract: A programmable delay circuit with a simplified structure conserves parts and provides for simplified programmability. In this structure, N delay stages (1-N) each include delay elements (10,26, . . . ,80) that produce delay times that are related as powers of two and are connected by two-input multiplexers (12,22, . . . ,82). The two-input multiplexers select between the input and output of the delay element in their stage, and are collectively controlled by N-bits of delay selection signals that are connected so that less significant bits control multiplexers associated with delay elements producing shorter delays and more significant bits control multiplexers associated with delay elements producing longer delays in a monotonic correspondence. The resulting structure conserves parts and produces an overall delay time that is directly proportional to the binary value used to control the multiplexers.

Abstract: Apparatus for manipulating numerical values stored in a memory comprises a modify device for receiving numerical values from the memory and returning numerical values to the memory. The modify device has at least a first state in which it modifies a numerical value received from the memory in a predetermined fashion before returning the numerical value to the memory and a second state in which it does not modify a numerical value received from the memory in the predetermined fashion before returning the numerical value to the memory. The apparatus also comprises a characterizing device for examining at least some of the numerical values and calculating at least one number that defines a property of the examined numerical values. The characterizing device is connected to the modify device for placing the modify device in the first state or the second state depending on the value of the calculated number.

Abstract: A thermometer-to-binary encoder includes a set of J input stage encoders E(1) through E(J) and an output encoder D, where J= 2.sup.K is an integer greater than 1. A set of digital input signals each representing a separate bit of a thermometer code T is grouped into J signal subsets representing further thermometer codes T(1) through T(J) providing inputs to a set of input stage encoders E(1) through E(J) respectively. Encoder E(J) produces an N-K+1 bit output binary code B(J) representing thermometer code T(J). Encoders E(1) through E(J-1) produce M-bit output binary codes G(1) through G(J-1), respectively, comprising the lower M bits of a binary code representing thermometer codes T(1) through T(J-1), respectively, where M is an integer greater than 1. Output encoder D processes codes G(1) through G(J-1) and B(J) to produce a set of digital output signals representing a binary code Y representing input thermometer code T.

Abstract: An auto selecting scrolling device is an improved user interface for viewing and making selection of a parameter from a menu. When a device, used to scroll through a menu, is activated the menu appears. A timer with user preset time limit is started. As long as the scrolling device is being used to scroll through the parameters in the menu, the timer is reset. While the scrolling is taking place the parameters are not only highlighted but also magnified. If the menu is no longer being scrolled through, then the timer expires upon attaining the user set limit. When the timer expires, the last highlighted parameter is selected and the menu is closed.

Abstract: A method allows analog device model descriptions to be described in a suitable language and then automatically converted into the language of the simulator in a form that facilitates gradient-based calculations. The method can include the steps of: entering a high-level description of the component model by naming the model, declaring parameters, specifying argument-independent equations, describing a topology of the model, declaring arguments, and specifying argument-dependent equations.

Abstract: An improved sample and hold signal generator produces very short delay intervals between successive sample-to-hold transitions that are both collectively and individually adjustable. A plurality of capacitors are charged to a precharge level upon the occurrence of a precharge signal and discharged to the threshold level of a plurality of amplifiers through a plurality of constant current sources upon the occurrence of a discharge signal. When the voltage on a particular capacitor is discharged to the threshold level, the associated amplifier produces a sample-to-hold signal transition and the voltage level of a signal being sampled is stored on a capacitor. In successive cells of the sample and hold generating means the threshold level is reached at incrementally varying delay times that are separated by approximately equal time intervals.

Abstract: An apparatus and method for dynamic memory allocation conserves memory resources while providing efficient and effective interaction between concurrent synchronous and asynchronous acquisition of data for logic analysis. The apparatus includes circuitry for acquiring synchronous data, circuitry for acquiring asynchronous data, circuitry for generating timestamp values, circuitry for determining when the synchronous data is valid, circuitry for determining when the asynchronous data is valid, and circuitry for packing valid synchronous data and valid asynchronous data into a memory according to the sequence in which it was acquired with sufficient timestamp values included to permit reconstruction of the relative timing between all of the acquired data, with each data and timestamp value being identified with status bits to indicate whether it was synchronous data, asynchronous data, or a timestamp value.