Abstract: A finite impulse response (FIR) digital filter (100, 170, 175, 180) incorporates both symmetric and transposed structures in a configuration that suites ASIC implementation. The filter coefficients can be arranged in ascending order to implement coefficient block floating point, or in descending order. To further facilitate coefficient block floating point, filter coefficients are chosen so that each cell has an exponent value equal to or greater than that of a preceding cell. A right shift is provided between adjacent cells to equate the exponent value of a sum output of a preceding cell with that of the succeeding cell. Variable decimation is provided by downloading appropriate filter coefficient and adjusting a decimation forward clock. Multiple channels can also be accommodated.

Abstract: A digital data generation system including a programmable dominance RS flip-flop has a random access memory that stores a user selected sequence of test data. A pattern formatting logic circuit receives the test data and produces, for each data period, a coarsely timed candidate pulse for identifying the leading edge of an output data pulse and a coarsely timed candidate pulse for identifying the trailing edge of the output data pulse. A precision delay circuit finely tunes the timing of the candidate pulses. The finely tuned pulses are applied to an RS flip-flop circuit which can be programmed for set or reset dominance, thereby preventing an indeterminate state when a logic "1" is applied to both the set and the reset input. In the system, the flip-flop is programmed so that the most recent of the lead pulse or the trail pulse prevails.

Abstract: A translinear f.sub.T multiplier has a pair of differential transistor amplifiers, each pair having commonly coupled emitters, with the base of one transistor of one pair being coupled to the base of one transistor of the other pair and the collectors of the pair being cross-coupled. A diode network provides three parallel diode paths from a reference voltage, two paths being coupled to receive an input signal and to the bases of the other transistors of each pair and the third path being coupled to a constant current source and to the bases of the first transistors of each pair. The resulting circuit configuration accommodates varying transition times.

Abstract: A CMOS-compatible peak detection circuit includes a differential amplifier stage (10), an active peak holding circuit (12), and a passive peak holding circuit (14). The differential amplifier stage (10) produces an amplifier output signal that is responsive to the difference between an input signal being monitored and feedback from the active peak holding circuit (12). Both the active peak holding circuit (12) and the passive peak holding circuit (14) store a charge representing a voltage level that is indicative of the peak amplitude of the amplifier output signal during a time interval, the time interval occurring while a disable signal is inactive. The active peak holding circuit (12) provides the maximum value signal as feedback to the differential amplifier stage (10). The passive peak holding circuit (14) provides a max signal output corresponding to the maximum value to a voltage follower stage (16) that makes it available as an output when a readback enable signal goes active.

Abstract: A fast, CMOS-based peak detection cell circuit and related methods can be used to determine maximum and minimum excursions of a signal being monitored during the very short intervals between high speed sampling points. Two nodes, "a" and "b", of such a circuit are precharged. Node "a" is then connected to the signal to be monitored. A PMOS transistor, with node "a" on its gate and node "b" on its drain, then causes a capacitance at node "b" to discharge to the voltage level of node "a" plus a constant offset voltage. Node "b" thus tracks downward excursions of the signal to be monitored, but not upward ones. Therefore, the voltage level at node "b" at the end of the acquisition interval is a function of the lowest voltage level assumed by the signal. A trio of such minimum detection cell circuits can be used together to find minimum and maximum behaviors of a differential complementary pair of signals.

Abstract: An integrated oscillator includes an amplifier having first and second voltage inputs, and first and second current outputs, and a current mirror having an input coupled to the second current output of the amplifier and an output coupled to the first current output of the amplifier. The output of the current mirror and the first current output of the amplifier are coupled through a bonding pad to an external capacitor. A first comparator has a first input coupled to the first current output of the amplifier and a second input for receiving a first threshold voltage, and a second comparator has a first input coupled to the first current output of the amplifier and a second input for receiving a second threshold voltage. A flip-flop has a first input coupled to the output of the first comparator, a second input, and an output coupled to the second voltage input of the amplifier.

Abstract: An all NPN transistor level-shifting differential amplifier has first and second identical amplifier halves, in which each amplifier half includes a passive voltage-shifting network coupled between a load and a current source. A main amplifier has a single-ended voltage input and an output coupled to the first node of the voltage shifting network. An output amplifier has a single-ended current output and an input coupled to the second node of the voltage shifting network. The main amplifier and output amplifiers are coupled together such that a portion of the bias and signal currents flowing through the output amplifier is reused and flows through the main amplifier, reducing bias current and power requirements. The first and second amplifier halves are coupled together with a gain-setting emitter resistor. In addition to reducing the power requirements of the amplifier, the feedback configuration of the level-shifting amplifier also increases linearity over prior art level-shifting amplifiers.

Abstract: A multi-channel analog-to-digital converter includes a counter (20) and a plurality of analog-to-digital conversion cells (10), each of which contain incremental discharge means (11-16) that store a charge proportional to the voltage value of an analog input signal and discharge that charge in increments upon the occurrence of the clock signal, also producing an active signal after the charge has been stored and before the incremental discharge is complete. A register (17) receives a count signal from the counter (20) and stores its value when the active signal goes inactive. A multiplexer (18) selects among the outputs of the plurality of analog-to-digital conversion cells (10) and supplies the selected output as a digital output signal.

Abstract: A single loop analog-to-digital conversion and video clamping circuit includes a low-pass filter and analog amplifier that present the incoming analog video signal to an analog-to-digital converter and to the input of a limit detector and protection circuit. The output of the analog-to-digital converter is sampled an integer multiple of four times during the black interval, with the results being summed and averaged. The resulting value is then scaled and limited, and compared to the desired level for a representation of black. Any resulting error quantity is converted from digital back to, analog and modified if necessary by the output of the limit detector and protection circuit. The signal that results from that modification is low-pass filtered and converted to a current by a transconductance amplifier. The resulting feedback current is then applied to a capacitor in the input circuitry, thereby clamping the input and resulting digital output of the overall circuit to the desired level.

Abstract: A method of detection of metastability of a trigger in a digital storage oscilloscope compares a predetermined address used to produce a trigger ready signal with a current address determined by the occurrence of a trigger event after the trigger ready signal. If the difference between the two addresses is within a predetermined limit, a metastable condition is indicated, and data acquired is treated as corrupted data.

Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: An improved circuit simulator interface permits a user to define one or more output parameters describing behavior of hierarchically-defined subcircuits of a circuit. The user defines each output parameter by a hierarchial expression including one or more primitive output parameters generated by a simulator when simulating the circuit or other user-defined output parameters describing behavior of subcircuits of the circuit. Once the circuit simulator has simulated the circuit and has generated the primitive output parameter values, the simulator interface responds to a user request to display the value of a selected user-defined output parameter by decomposing the hierarchical parameter expression defining the selected output parameter to an expression combining only primitive parameter values. The simulator interface then evaluates the decomposed expression using primitive parameter values generated by the simulator and displays the result.

Abstract: A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing control signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

Abstract: A method and circuit for triggering an electronic instrument only once during a period of an input signal having multiple triggering events during that period. A signal applied to an electronic instrument, such as an oscilloscope, is acquired. Qualified triggering events occurring on the acquired signal are identified. A selected one of the qualified triggering events during the period of the applied signal causes a trigger signal output to occur, while other qualified triggering events are ignored. In the preferred embodiment a triggering event is qualified by a first comparator that compares the input signal to a first reference level and produces a predetermined logic level output if the input signal bears a predetermined relationship to the reference level. When a qualified triggering event occurs, a buffer amplifier applies the predetermined logic level to charge a capacitor, which thereafter stores some energy from the input signal and applies it to a comparator for a predetermined period of time.

Abstract: A digital architecture for a pulse generator provides a method of synchronizing signals of the pulse generator. The pulse generator has a timebase card, a microprocessor and a plurality of pulse cards. The microprocessor controls the parameters of the timebase card and pulse cards, and the timebase card provides a common master clock signal to all of the pulse cards determined by a triggerable voltage controlled oscillator that has two sources of frequency control voltage, an internal DAC for absolute frequency and a frequency comparison circuit for synchronization with an external timebase. The pulse cards produce pulses, either singly or in bursts, with the leading and trailing edges being separately positionable using quantum, sliver and vernier controls. A pattern RAM on each pulse card provides a pulse pattern that provides an approximation of the desired pulses to one quantum, and repeated iterations through the pattern RAM provide bursts of pulses.

Abstract: A sequence of events detector provides a way to continuously monitor serial digital data and precisely define the behavior that it must exhibit in order to qualify as the sequence of events that the user wishes to detect. A plurality of evaluation windows each sequentially examine the behavior of one or more signals, comparing this behavior with predefined criteria. Each evaluation window is activated to begin its portion of the overall evaluation process by a match signal from the preceding window, indicating that its predefined criteria were met. In one version, a sequence starting circuit activates the first evaluation window in response to an external signal or the occurrence of a predefined condition, and a multiplexer trigger source circuit selects as the overall detector output the match signal output of the last evaluation window used to define the overall sequence of events. In another version, each evaluation window explicitly reports a failure if its predefined criteria are not met.

Abstract: An apparatus and method for digitizing a repetitive waveform using an analog oscilloscope uses a successive approximation technique. For each sample point on the repetitive waveform a digitizing level is compared with the repetitive waveform at that sample point, and the digitizing level is adjusted until it essentially equals the magnitude of the repetitive waveform at that point. The particular sample point is determined by comparing a delay level with a ramp signal that starts from an initial fixed trigger point on the repetitive waveform. Each point is digitized in this manner in one of three modes. The first mode samples the same point on successive iterations of the waveform until that point is digitized, and then the next point is digitized. The second mode samples each point once per iteration of the waveform by stepping the delay level n times during each iteration, and adjusting the digitizing level individually for each sample point until the digitization is complete.

Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: An attenuator assembly (38) employs circuitry formed on an attenuator substrate (44) having short voltage divider path lengths that allow the use of low-cost divider selecting relays (58, 60, and 62) while maintaining low VSWR and aberration levels through the attenuator. An interconnect circuit board (80) provides electrical power, control signals, a ground plane shield (108), and probe coding contacts (32) for connection to the attenuator substrate. The circuits on the attenuator substrate are laser-trimmed to obtain predetermined electrical characteristics prior to assembly in a completed attenuator assembly. The attenuator substrate rests on a recess (128) formed in top margin (127) of a cavity (120) formed within a housing (42).

Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.