Abstract: A high speed probe attenuator has an attenuator with a plurality of resistors connected in series between a probe input and an instrument output. A plurality of capacitors are coupled in parallel with pairs of the resistors in an interleaved fashion to spread the frequency correction along the attenuator. The output of the attenuator is coupled by a large diameter coaxial cable to a test instrument. The result is a high speed probe with no dribble-up effect and no overshoot.
Abstract: A pinch clip lid for a non-hermetic package containing an electronic component having an exposed face has a step lid that includes means for centering the lid on the package. Attached to opposing sides of the lid are side bars that have a lower portion that extends slightly inwardly to grip the package when the lid is mounted on the package, and that have an upper portion contiguous with the lower portion so that when the top portions are pinched, the lower portions release the grip on the package so that the lid may be removed from or placed on the package.
Abstract: A circuit for software performance analysis implements a balanced binary tree in hardware. This circuit consists of a number of "levels", each containing two (sets of) latches, a RAM, and a digital comparator. One of the latches, the data latch, is used to hold the data element being evaluated. The other latch, the results latch, stores partial results based on the comparisons performed on higher levels. The RAM is addressed by the contents of the results latch on the preceding level in combination with the output of the comparator on that same preceding level. The output of the RAM is compared by the digital comparator with the contents of the data latch, to produce an additional bit of results information for the next level. On each level, the RAM is preprogrammed with twice as many midpoint addresses as is the RAM on the preceding level. The outcome of the comparison done on any particular level is used, along with the results from preceding levels, as an address to access a RAM on the next level.
May 30, 1989
Date of Patent:
December 1, 1992
Dennis D. Everson, Philip R. Lantz, Stanley R. Koslowski
Abstract: An apparatus creates a "rainbow-like" effect in a decaying video afterimage by including a chrominance phase rotator within a recursive video effects loop, so that the hue of the afterimage is recursively altered as it decays. The chrominance phase rotator can be placed anywhere within the recursive loop, and can also be combined with a blurring effect and/or the decay factor multiplication needed for the basic recursive circuit. Several variants of the circuitry for providing chrominance phase rotation are provided; some suitable for processing cosited chrominance components, others suitable for processing noncosited chrominance components. Additional variations conserve the number of parts required at the expense of technical color accuracy by making simplifying assumptions.
Abstract: A chrominance filtering system reduces chrominance detail when sufficient luminance detail is present, but limits how much chrominance detail is reduced when insufficient luminance detail is present. The chrominance input signal is applied to a high pass filter and a suitable delay circuit. The output of the high pass filter, C.sub.hp, is a signal indicative of chrominance detail. It is applied to the input of a bipolar clipping circuit that also receives a control signal, .vertline.Y.sub.hp '.vertline..sub.clipped indicative of luminance detail. The control signal is derived by high pass filtering, rectifying and low pass filtering the luminance signal to produce a signal, .vertline.Y.sub.hp .vertline., that is absolute value of high pass filtered luminance activity. This signal is then scaled by multiplication by a first constant and then offset by addition to a second constant to produce .vertline.Y.sub.hp '.vertline.. .vertline.Y.sub.hp '.vertline.
Abstract: A multiple section cable equalizer with a signal level detector produces a clipping control signal for amplifiers in each equalizer section, so that a variable level input signal is restored to an equalized output signal that is free of distortion and attendant bit errors. A fixed reference clipping stage after the last equalizing stage produces a signal clipped to a final output level. A feedback path restores DC and low frequencies lost due to AC coupling. A test output stage permits monitoring of the operation of the equalizer stages. The signal level detector contains (in series), a differential amplifier with low pass filtering, a balanced modulator detector, a voltage amplifier, a comparator and peak detector, a transconductance amplifier and a plurality of current mirrors operatively connected to determine a difference current from the output of the transconductance amplifier and convert this to a clipping control signal voltage level.
Abstract: The present invention is a method and an electrical circuit (28 and 50) for effectively eliminating the effects of time jitter caused by metastable states by rejecting measurements made under timing conditions that could lead to the development of metastable states. In a preferred embodiment, the circuit of the invention effectively eliminates time jitter caused by metastable states in digital oscilloscope circuitry by determining in advance the timing conditions that can lead to such jitter and detecting whenever the transitions of trigger and trigger hold-off signals meet such timing conditions. The circuit then generates a "possible metastable" signal that can be used by the oscilloscope circuitry, or by the controlling software, to reject any measurement made under those timing conditions.
Abstract: A method and apparatus prevents unwanted synchronization from obstructing a data acquisition instrument operator's view of N multiplexed signals synchronized to a high speed system clock being used to trigger an instrument through a prescaler with a fixed prescaling factor M, where N and M are related by a common factor. During a time while the instrument, for example, an oscilloscope, is ignoring trigger input information, a desynchronizing signal is applied to the prescaler, causing it to miss a random number of counts or causing it to count incorrectly. Thus, when the oscilloscope resumes triggering it is likely to be synchronized to a different combination of the multiplexed signals. This technique can be applied to individual data points or to records containing a number of data points.
Abstract: An improved marker and cursor system for spectral waveform measurement permits the operator to link or unlink a cursor and a marker, allowing them to be used separately or in coordination to make bandwidth measurements. A second reference marker permits measurement of the frequency and amplitude differneces between it and the marker at the same time that the marker is being used control the linked cursor. The cursor can be fixed or linked in a constant positive or negative delta-amplitude relationship to the marker. The points on the cursor where the cursor and spectral waveform intersect are intensified for identification and a readout is provided of the difference in frequency values between these points. Measurements continue even during unstable conditions of the instrument or spectral waveform and fluctuations show up as only minor movements of the intensified points along the cursor.
Abstract: A method and apparatus for determining the internal state of a processor without disturbing the operational environment of the processor employs a two phase process. In the first phase, external signals produced by the processor in the execution of a known program are monitored and recorded for subsequent analysis. In the second phase, the recorded information is analyzed in the light of the known characteristic of the processor, the program it was executing, and the signals recorded during the first phase. The internal state of the processor is thereby determined after the execution of each instruction. In addition, provisions are made for the specification of breakpoints, and the examination of simulated status of the processor on the occurrence of the breakpoints.
Abstract: A voltage controlled reference oscillator with a high Q and narrow tunability bandwidth produces an output oscillator frequency which is frequency divided by four alternative constants to produce four different clock frequencies for four different digital video standards, D1 component at 270 MHz, NTSC D2 composite at 143 MHz, PAL D2 composite at 177 MHz, and a proposed new composite video standard that is to operate at a 360 MHz clock rate. Automatic identification of which serial digital video is present is accomplished by having the clock generator produce a clock signal at the frequency required by one of the video formats while a phase lock loop attempts to lock onto the incoming signals at that frequency. If no lock occurs within a predetermined time interval, the clock generator is made to produce a clock signal at the frequency required by a different one of the video formats and the phase lock is attempted again. This is repeated until a lock is attained.
Abstract: As frequency spectra are produced continuously at a speed that is too fast for realtime display, they are accumulated in a memory. After a block of these frequency spectra have been accumulated, they are read back from the memory and displayed on a display device that permits the display of multiple frequency spectra along a time axis. Markers allow delta-time measurements to be made between different spectra in the display. Continuous storage into a circular memory can be stopped and the display of the accumulated frequency spectra started by the detection of the occurrence of a pre-defined spectra event.
Abstract: An apparatus for counting the number of times that each of a large number of digital data patterns are present on a set of signal lines comprises a plurality of random access memories (RAMs) and a feedback means, arranged to form an array of linear feedback shift registers. The data to be analyzed is applied to the address inputs of the RAMs where it selects one of the linear feedback shift registers in the array. A data-valid signal associated with this data causes the selected linear feedback shift register to increment (or decrement) in its pseudo-random count. After the analysis period is over, the value at each address is read out and translated using a lookup table or other translating means from the pseudo-random code of the linear feedback shift register into a meaningful number. This result may then be displayed; for example, in a histogram. An improved feedback path for the linear feedback shift register avoids hang-up states and the need for initialization.
Abstract: A method and apparatus are disclosed, that is suitable for digital or analog spectrum analyzers, for accurately and rapidly ascertaining the frequency of a spectral line by determining its location from the response of two Gaussian shaped filters whose center frequencies bracket the frequency of the spectral line. The difference is taken between the amplitudes in decibels of the responses of the two Gaussian filters to the spectral line input signal. The frequency of the spectral line is then found from the linear relationship fx=delta-log-ampl.*c1+c2, where c1 is proportional to the square of the standard deviation of the Gaussian filters and inversely proportional to the difference between the center frequencies, f1 and f2, of the Gaussian filters times the logarithm of e, and where c2 is the midpoint between the center frequencies, f1 and f2, of the Gaussian filters, G1 and G2.
Abstract: An output driver circuit of the type having two transmission gates, which are preferably CMOS transmission gates, is improved by inserting a variable, and preferably digitally programmable, pulse stretcher in the path of both the high-enable and the low-enable signals that open and close the high-side and low-side transmission gates. The variable delay element of the pulse stretcher can be set to an optimum delay by an "empirical" procedure that entails applying a series of pulses of incrementally varying duration to the output driver circuit, while monitoring the quality of waveform that they produce. A few of these waveforms will be distorted as a result of the impedance mismatch. The variable delay element of the pulse stretcher is then repeatedly adjusted. For each value of variable delay, another series of pulses of incrementally varying duration are again applied to the output of the driver circuit while the quality of the waveforms produced is monitored.
Abstract: A logic analyzer stores the activity around the last in a series of triggering events while also storing the activity around several other triggering events immediately preceding the last trigger. The acquisition memory is first positioned into a number, N, of memory sections and the trigger condition of interest is defined. Then repeated acquistions are performed using this same trigger condition. At first, data from each of these acquisitions is stored in each one of the number of memory sections. When all of the memory sections have been filled once, if the trigger condition is still occurring, the acquisition memories are reused in the same order in which they were originally used as many times as necessary until it is ascertained that the trigger condition is no longer occurring or some external conditon has changed, at which time the logic analyzer is stopped. One of the memory sections then contains the data that occurred in the vicinity of the last trigger.
Abstract: A graphics path display has fixed wireframes representing key positions of an image being manipulated. Inbetween wireframes, dots or dashes are generated according to a defined display rate between sequential key positions. The inbetween wireframes are generated by an algorithm selected by an operator, and are adjusted in realtime as the operator changes variable parameters for the algorithm to present a realtime display of the graphics path defined by the algorithm and parameters.
July 17, 1989
Date of Patent:
October 1, 1991
The Grass Valley Group, Inc.
Richard A. Frasier, F. Andrew Witek, Charles Q. Hoard, Neil R. Olmstead, William C. Lange
Abstract: A method for generating a stimulus signal for conducting frequency response function calculations maximizes the overall dynamic range of the calculations possible by balancing the requirements for dynamic range between the input channels of a Fourier analyzer used for monitoring the input and output of the system under analysis. A preferred version of the method includes the steps of estimating the frequency response function of the system under analysis, inverting the estimated frequency response function, taking the square root of the inverted estimated frequency response function, randomizing the phase of the inverse square-root estimated frequency response function, converting the phase-randomized inverse square-root estimated frequency response function to a time domain test signal, scaling the time domain test signal as necessary to produce the stimulus signal for conducting frequency response function calculations.
Abstract: A method for performing signal quality analysis on digital signals uses simultaneous dual threshold data acquisition. Using this method, the data need not be repetitive and, because the reference data and the variable data are acquired simultaneously, the logic analyzer continues to trigger and further measurements can be made after significant noise has been encountered. One threshold is designated the reference threshold and used to perform triggering and acquisition of reference data, while the other threshold is designated the variable threshold and used to acquire data for the noise margin analysis. At each increment of variable level, the data acquired by the reference acquisition and the data acquired using the variable threshold level is compared to see at what point in time and on what signal lines noise begins to affect the quality of the data.
Abstract: A phase-selectable flip-flop has an input dual-enable transparent latch and an output D-type flip-flop. A clock is input to one enable of the transparent latch and to the flip-flop, and a command is input to the second enable of the transparent latch. When the command is in a first state the latch is held transparent and data is clocked into the flip-flop on the rising edge of the clock, and when the command is in a second state data is held by the transparent latch on the falling edge of the clock and clocked into the flip-flop on the succeeding rising edge.