Abstract: A low profile hermetic electrical connector includes a conductive layer with opposite first and second conductive layer surfaces. An inner electrical isolation layer is coupled between the first conductive layer surface and a first contact and an outer electrical isolation layer is coupled between the second conductive layer surface and a second contact. A contact interconnector electrically couples the first contact and the second contact through the inner electrical isolation layer, the conductive layer, and the outer electrical isolation layer without electrically contacting the conductive layer, creating a serpentine, low flow path for vapor through the adhesive layers. In a hermetic electrical cable end connector, the first contact is electrically coupled to a first conductor through a first interconnector and a second contact is electrically coupled to a second conductor through a second interconnector. Two additional electrical isolation layers are required.

Abstract: A method for designing and making an RF transformer has been provided. The method utilizes a model for an RF transformer wherein the model has parameters that directly relate to a physical construction of the components of the transformer, namely, a core and a twisted wire. The method separates the core from the twisted wire so that characteristics of each can be separately determined. These determined characteristics are then optimized and used to design and make a transformer.

Abstract: A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

Abstract: An impedance transforming power divider/combiner includes a first transmission line (60) with a first terminal (65) and N transmission line fingers (65, 66, 68, 70) terminating in N transmission line finger ends. N transmission lines (28, 38, 48, 58) having N first and second ends are positioned in close proximity to the N transmission line fingers (65, 66, 68, 70) in one-to-one correspondences. The N second ends of the N transmission lines (28, 38, 48, 58) are coupled through N individual impedances (20, 30, 40, 50) to N terminals (25, 35, 45, 55). If signal power is provided to the first terminal (64), the signal power is divided into N signal power outputs at the N terminals (25, 35, 45, 55). If signal power is provided to the N terminals (25, 35, 45, 55), a combined signal power results at the first terminal (65).

Abstract: A multilateration location system (12) includes a locatable unit (16) and any number of known-position locators (14). A time of arrival detector (22) determines instants in time when a location signal (20) transmitted by the locatable unit (16) arrives at various known-position locators (14). For each combination of two known-position locators (14) that receive the location signal (20), a pre-estimation process (32) determines whether the difference in arrival times is less than or equal to a maximum propagation duration for the locator pair. The maximum propagation duration is based upon the distance between the locators (14) in the locator pair. If the difference is greater than the maximum propagation duration, the difference is omitted from the data set processed by a multilateration calculation process (34). A post estimation filtering process (36) screens out location estimates that are too distant from a predicted position.

Abstract: A technique for achieving impedance transformations utilizing transmission lines has been provided. This technique involves placing additional distributed capacitance along the length of a transmission line thereby reducing the effective characteristic impedance of the transmission line. The effective wavelength for the transmission line is also reduced thereby substantially reducing the electrical length of a quarter wavelength matching network and making the transmission line practical and effective even at low frequencies.

Abstract: An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.

Abstract: A MMIC FET mixer and method includes a RF input port for receiving a RF signal, a feedback control input for receiving a feedback signal, and a LO input port for receiving a LO signal. A feedback controller is coupled to the RF amplifier, the feedback controller for producing a controlled RF signal in response to the feedback signal. A constant current source is coupled to the feedback controller, to the RF amplifier and to the LO input port. The constant current source receives a DC offset voltage, the controlled RF signal, and the LO signal and produces an IF output signal at an IF output port. The IF output signal is proportional to the DC offset voltage, to the RF signal, and to the LO signal.

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract: A circuit (10) for enhancing logic transitions appearing on a line (34) has been provided. The circuit includes a first comparator (14) for sensing when a voltage on the line exceeds a first level and subsequently pulling the voltage on the line to a first predetermined voltage. The circuit also includes a second comparator (12) for sensing when the voltage on the line falls below a second level and subsequently pulling the voltage on the line to a second predetermined voltage.

Abstract: A non-intrusive mounting system and method for coupling microwave instruments to a container flange having an opening into a container. The mounting system includes a microwave transparent window and a mounting flange having a window recess for accommodating the microwave transparent window. The microwave transparent window is compressively fastened over the container opening between the mounting flange and the container flange. Microwave instruments such as radar level sensing apparatus can be mounted on and removed from the mounting flange without breaking the seal to the container.

Abstract: A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for quickly switching on the power transistor. However, once the power transistor is turned on, the first stage becomes inactive and a second stage (16) coupled to a second supply voltage terminal provides a low current drive signal to the power transistor for fully enhancing the power transistor and lowering its on resistance. The gate drive circuit further includes a timer circuit (18) for rendering the first stage active for predetermined period of time.

Abstract: A voltage controlled oscillator (VCO) (2) provides an output signal which has a 50% duty cycle and a frequency which depends on the voltage of a control signal (V) supplied thereto. The VCO (2) comprises first (C.sub.L) and second (C.sub.R) capacitors and first (3) and second (5) circuits. Each of the first and second circuits comprises a current supply arrangement (10, 12, 14, or 18, 20, 22) coupled to a respective one of the capacitors (C.sub.L or C.sub.R) and to receive the control signal (V), and a Schmitt trigger (6 or 16) coupled to the respective current supply arrangement and to the other capacitor, which is not coupled to the respective current supply arrangement. Each current supply arrangement of the first and second circuits alternately charges and discharges the respective capacitor, in dependence on the switching of the respective Schmitt trigger, so that the VCO (2) oscillates between the charging of the first and the charging of the second capacitor.

Abstract: A control circuit for switching AC or DC loads and for automatically discerning the presence of an AC or a DC power supply via a switch has been provided. The control circuit is coupled to alternately render a switch operative and non-operative wherein the switch is coupled across a load which is powered up by either an AC or a DC power supply. The control circuit includes an AC/DC discernment circuit for ascertaining whether the load is powered up by an AC or a DC power supply. The control circuit also includes circuitry for comparing signals sensed by the switch with predetermined thresholds (which are a function of whether an AC or DC determination has been made) for providing logic signals to control the operation of the switch.

Abstract: A detection circuit for sensing small capacitive changes has been provided. The detection circuit includes a dummy integrator stage that compensates for a voltage step that results from charge injection due to an existing switch in a first integrator stage. As a result, the detection circuit is insensitive to switch injection and amplifier offset voltages.

Abstract: An active filter circuit (10) that has a cut off frequency being substantially independent of absolute and temperature variations due to on chip resistors (R.sub.1, R.sub.2 and R.sub.3) has been provided. The active filter includes a transconductance gain amplifier (16) having first and second currents (I.sub.B and I.sub.E) the ratio of which are controlled such that the absolute and temperature effects of any on chip resistors of the active filter circuit are removed. The ratio of the first and second currents of the transconductance gain amplifier are controlled by a circuit that generates third and fourth currents (I.sub.b and I.sub.e) which are a function of a bandgap voltage. The circuit then utilizes the third and fourth currents and provides, to the transconductance gain amplifier, a current that is substantially equal to the ratio of square of the third current to the fourth current, and a current substantially equal to the fourth current.

Abstract: The present invention provides an amplifier arrangement to which feed forward correction is applied by a comparison loop including comparison means for comparing amplifier input with amplifier output to provide an error signal, a cancellation loop including secondary amplifier means for amplifying the error signal and combining means for combining said amplified signal with said amplifier output, a pilot generator coupled to said amplifier input to introduce a pilot tone therein, detector means for detecting a level of pilot tone in said amplifier output and correction means for correcting said cancellation loop performance as a function of said detection wherein said pilot generator is further coupled to a multiplier receiving said amplifier output, said multiplier producing an output signal arranged to control a loop parameter to effect said correction.

Abstract: A speakerphone with a varying gain current mirror circuit is provided. The varying gain current mirror circuit is within the DC control loop of the speakerphone such that by varying the gain of the current mirror circuit, the attenuation range of the speakerphone is correspondingly varied.

Abstract: A buffer circuit for programming an I/O pin of a programmable logic device to function either as a normal I/O site, a power pin, or a ground pin has been provided. The I/O pin may be programmed by a user by simply placing first and second control signals in appropriate logic states. The buffer circuit also includes a tri-state circuit for providing tri-state outputs when functioning as a normal I/O site.

Abstract: An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.