Abstract: A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

Abstract: A gain stage for providing an automatic phase shift is provided. In particular, the gain stage detects whether an oscillation signal appears at its inputs. If an oscillation signal is not detected, then the gain stage inverts output signals occurring at outputs of a first amplifier before being respectively applied to inputs of a second amplifier. This has the overall effect of implementing a 180.degree. phase shift of a signal appearing at the outputs of the gain stage with respect to a signal appearing at the inputs of the gain stage.

Abstract: A circuit for a pulse width modulating a sensor (12) has been provided. The circuit includes a first switch (22) for alternately coupling the sensor between first and second supply voltage terminals. The circuit also includes second (24) and third (28) switches and first and second capacitors for sampling the differential voltage appearing at outputs of the sensor when the first switch is in a closed state.

Abstract: A circuit for detecting when a fault condition has occurred includes an input stage responsive to a logic signal supplied to an input of the circuit for providing an output logic signal at an output thereof. An output stage, including a pulldown circuit, responsive to the output logic signal of the input stage, for providing an output logic signal at an output of the circuit. A fault detection circuit coupled to the output of the input stage and to the output stage for forcing the output of the circuit to a predetermined logic state when the pulldown circuit of the output stage is defective.

Abstract: A control circuit for protecting a power device has been provided. The control circuit has a thermal shutdown circuit for activating a first SCR when the temperature of the control circuit exceeds a predetermined temperature. Additionally, the control circuit has a DSAT detection circuit for activating the first SCR in response to an external signal. The first SCR is coupled across an input terminal and the common terminal of the control circuit. When the first SCR latches, it functions to subsequently latch a second SCR that is coupled across the output and common terminals. The second SCR functions to rapidly discharge the voltage appearing across the output and common terminals.Additionally, the control circuit includes an input level sensitive circuit which may be utilized to deactivate various circuitry depending upon the current level of an input signal supplied to the control circuit.

Abstract: A block architected integrated circuit having a predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures.The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit.

Abstract: An AGC system for use in positive modulation schemes of video signals is provided. The AGC system utilizes an IF amplifier, a demodulator, a video amplifier, a gated amplifier and a peak detector. The gated amplifier has a first, relatively fast, time constant associated therewith. The gated amplifier, which is activated during the time interval that the black voltage appears on the video signal, is responsive to an intial reference voltage and to the video signal for providing an output signal to control the gain of the IF amplifier. The peak detector has a second, relatively slow, time constant associated therewith. The peak detector is used to detect the peak white voltage level of the video signal to adjust the initial reference voltage to account for fluctuations and errors in the peak white voltage level.

Abstract: An output driver stage (10) having current limit protection has been provided. The output driver stage provides current protection for both itself and for an output load which may be coupled to an output terminal (12). The current limit protection is accomplished via a one shot timer (28) which controls the charge at the output terminal. Further, the one shot timer may be activated by a plurality of output stages which respectively control a plurality of output loads.

Abstract: A current mirror circuit that can be disabled has been provided. An enable signal is applied to the base of a transistor that drives the common bases of an emitter-coupled pair of transistors. A voltage level of the enable signal may be used to turn off the transistor which subsequently turns off and disables the emitter-coupled pair of transistors.

Abstract: A protection circuit for providing short-circuit protection for a field effect transistor has been provided. The protection circuit senses when the voltage appearing at the gate and drain electrodes of the field effect transistor are both at a logic high voltage level, and responds to turn off the field effect transistor thereby preventing damage to the field effect transistor.

Abstract: A voltage controlled oscillator (VCO) circuit having a cascoded output stage has been provided. The VCO circuit includes an oscillation stage which utilizes a negative resistance technique for oscillation, and an output stage that is coupled in cascode with the oscillation stage thereby minimizing the power dissipation and allowing the output resistance of the VCO circuit to be adjusted for maximum drive capability.

Abstract: A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state.

Abstract: A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized to clock a plurality of serially-coupled flip-flops wherein two-times the input data signal is applied to the data input of the first serially-coupled flip-flop. The outputs of the serially-coupled flip-flops are ECL signals which are then translated to CMOS level signals via ECL-CMOS translators. Finally, the output signals of the translators are respectively used to clock divide-by-two configured flip-flops in order to provide the plurality of precise, phase shifted CMOS output signals. The plurality of precise, phase shifted, CMOS output signals have a 50% duty cycle and represent phase shifted versions of the input data signal wherein the minimum time delay between signals is substantially equal to the period of the precise clock signal.

Abstract: A LCD vertical scrolling mechanism automatically tracks addresses of information scrolled on a LCD. A counter is initialized to a value latched in a vector register when a frame signal is received. Subsequent BPCLK signals step the adder through a series of values. These values are relayed through two bus selectors to segment drivers for the LCD. One of the bus selectors is coupled to the counter in parallel with a subtracter. When a value from the counter exceeds a predetermined value equal to the MUX of the LCD, the subtracter takes the difference between the predetermined MUX value and the value received from the counter and directs the parallel bus selector to relay the difference to the RAM of a segment driver. An adder is coupled to the other bus selector and to the vector register. When the MCU needs to fetch information from the segment drivers, the MCU relays a LCD address where the information is displayed, to the adder.

Abstract: A driver for a stepper motor including means (Q45, 45, 47, 402) for sampling the current in a motor winding (43) at an instant determined by means (401, 400)for generating a predetermined delay following winding commutation. The sample is compared with winding current by a comparator (403) the output of which is stored at a subsequent instant in a flip-flop (416) to provide an output (42). Current generated within the windings due to rotor motion provide a difference in output when the motor is running or blocked. The invention provides a solution to the problem of motion detection of a stepper motor without recourse to a positional sensor.

Abstract: An on-chip self-test circuit has been provided that allows for accurately testing a device such as prescaler at high frequencies. The on-chip self-test circuit includes a voltage controlled oscillator for providing high frequency signals to the device under test.The on-chip self-test circuit is rendered active only when one desires to test the device. Thus, when not testing, the on-chip self-test circuit is transparent to the device and consumes substantially zero power.

Abstract: A circuit for producing a display indicative of a bicycle rider's pedaling technique. The circuit measures the time required for the pedals to move through a given angle of rotation. The circuit then calculates the relative pedal velocity over the angle of rotation. This process is repeated over an entire circle of rotation to determine the variations in pedal velocity as the pedal moves through a full circle. Since the pedal velocity is related to the pedaling force applied by the rider, the variations in pedaling force can be determined. Further, the circuit has a display unit which shows a rotating line of varying length to indicate the pedaling force applied as the pedals move respectively through a full circle.

Abstract: A logic circuit for testing the reliability of an ASIC includes an array circuit having a plurality of matrix arrays each having a plurality of inputs. The plurality of matrix arrays being positioned in a predetermined row and column of the array circuit and being responsive to a plurality of input signals applied thereto for providing a respective row and column output. A parity circuit responsive to the row and column outputs of the plurality of matrix arrays for causing an output signal at an output of the logic circuit to be in a first logic state whenever the row outputs of the plurality of matrix arrays are logically different, or whenever the column outputs of the plurality of matrix arrays are logically different. A stimulus circuit coupled to the plurality of inputs of the plurality of matrix arrays for supplying the plurality of input signals to exhaustively stimulate each one of the plurality of matrix arrays with all possible logic combinations.

Abstract: A charge pump circuit (10) has been provided for maintaining the currents sunk by each of the bottom current sources (12, 14) substantially equal to the current sourced from a first upper current source (16). The present invention maintains the voltage across a second upper current source (64) that determines the current for the lower current sources to be modified with respect to corresponding changes in the first upper current source wherein these changes in the first upper current source are due to a varying voltage occurring at the output (18) of the charge pump circuit.

Abstract: A telephone line card circuit includes an operational amplifier circuit having first and second inputs and an output. A field-effect transistor circuit has first, second and control electrodes, the control electrode is coupled to the output of the operational amplifier circuit, the first electrode is coupled to the TIP/RING terminal, and the second electrode is coupled to the second input of the operational amplifier circuit. A first resistor is coupled between the TIP/RING terminal and the first input of the operational amplifier circuit. A second resistor is coupled between the first input of the operational amplifier circuit and a terminal of the circuit whereby the terminal of the circuit is typically coupled to a supply voltage terminal.