Patents Represented by Attorney Brett N. Dorny
  • Patent number: 7079139
    Abstract: A method and system for measuring an object represented by a three dimensional model includes an algorithm for displaying the three dimensional object in a 2 dimensional space. Once rendered in two dimensions, a user can identify two points on the object in that two dimensional space and in accordance with the invention, the system can determine the distance between the two points in the three dimensional space of the object. The system and method can use a pick function to determine the coordinates of each point in three dimensional space as a function of the two dimensional coordinates of each point selected in the two dimensional display space and determine the distance between the three dimensional coordinates of each point in the three dimensional space.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: July 18, 2006
    Assignee: Kaon Interactive, Inc.
    Inventor: Joshua Edward Smith
  • Patent number: 6925632
    Abstract: In a development platform, a classifier for a given application defines a data model of an application model as a pattern (an object model) from a finite number of patterns (object models) that represent the possible permutations of data models. In addition, the development platform has a finite number of service objects that perform various functions/services on the object model from which the application model adopts one or more service objects. The object models and the service objects are generic to the development platform and usually a set of finite number of object models and a set of finite number of service objects can interface the application model with the various third party resources and tools.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: August 2, 2005
    Inventor: Martin Shiu
  • Patent number: 6867785
    Abstract: The present invention relates to a system and method for determining quality or resolution settings for encoding a three dimensional model within a desired size budget. The system allows the user to select or change the size budget and either the quality settings or resolution settings. The system, applying the method of the invention, then determines the resolution or quality settings for each image in the model so as to meet the size budget. The user may also lock certain settings so that they are not changed by the system when other modifications are made by the user.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: March 15, 2005
    Assignee: Kaon Interactive, Inc.
    Inventor: Joshua Edward Smith
  • Patent number: 6412428
    Abstract: A system for drying sludge includes a shaftless spiral feed screw for moving sludge through a drying chamber. An high energy inductor is located at a output of the drying chamber for drawing hot gases through the chamber to dry the sludge as it advances from the input end to the output end of the chamber. The high energy inductor also aspirates the dried sludge from the chamber. The drying system can be used in conjunction with a waste-to-energy furnace for incineration of sludge and municipal waste. In such an arrangement, the dried sludge can be aspirated from the drying chamber directly into a combustion zone of the furnace. Hot gases from the furnace can be used in drying the sludge.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: July 2, 2002
    Inventor: Vincent Promuto
  • Patent number: 5627483
    Abstract: A logic circuit has at least one first differential stage made of bipolar transistors operating in linear mode. The first differential stage is connected in a branch of a second differential stage biased by a current source. The second stage and the current source are made of MOS transistors.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: May 6, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Patrick Bernard, Didier Belot, Jacques Quervel
  • Patent number: 5624852
    Abstract: Integrated structure bipolar transistors with controlled storage time are manufactured by forming at least one bipolar transistor occupying a first area on a first surface of the silicon material, covering the first surface of the silicon material with an insulating material layer, and selectively removing the insulating material layer to open a window. The window has a second area much smaller than the first area occupied by the bipolar transistor. Therefore, by implanting into the silicon material a medium dose of platinum ions through the window and diffusing into the silicon material the implanted platinum ions, a uniform distribution of platinum inside the transistor is obtained.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: April 29, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventor: Ferruccio Frisina
  • Patent number: 5619543
    Abstract: A digital phase-locked loop filter in which the incoming error signals are subject to at least one multiplication by a filtering coefficient before being digitally processed at each clock pulse to provide a filtered signal. The PLL filter includes a circuit which decrements the value of the filtering coefficients at each clock pulse during an initial operation period of the filter.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: William Glass
  • Patent number: 5619451
    Abstract: A method for erasing a non-volatile electrically erasable and programmable integrated circuit memory that is divided into N sectors selected separately by addressing circuits and the cells for each sector being selected by row and column addressing circuits wherein an erasure pulse is applied simultaneously to all the sectors. The checking of the erasure of each sector leads to the locking of the sector when no defect is detected. A new erasure pulse is applied only to the unlocked sectors and only the unlocked sectors are rechecked. Also, a circuit for locking sectors in order to implement the method is disclosed.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Claude Costabello, Jean-Marie Gaultier
  • Patent number: 5615303
    Abstract: Circuit for calculation of values of membership functions in a controller operating with fuzzy logic procedures. The membership functions are of triangular or trapezoidal form and are defined in a so-called discourse universe discretized in a finite number of points. The controller includes a central control unit equipped with a memory section for storage of said membership functions, a microprocessor, and an interface. The membership functions are stored by means of a codification of the coordinate of the vertex and the slopes at the sides of the vertex. The circuit includes a calculator connected to the memory section, the microprocessor, and the interface, to determine the value of each membership functions at each point of the discourse universe using the stored vertex and slopes.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: March 25, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Massimo Abruzzese, Biagio Giacalone
  • Patent number: 5612641
    Abstract: A circuit for resetting initial conditions upon starting of an integrated circuit device has null current consumption under normal operating conditions. The circuit includes an input stage, which is a threshold circuit, and pilots through an input node an output stage which is a trigger circuit with hysteresis. The input node of the output stage is connected to ground through a condenser and is connected through a transistor to a connection node between a condenser and a diode connected transistor which are inserted between the power supply and ground. The gate terminal of the first transistor is grounded.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Mauro L. Sali
  • Patent number: 5612910
    Abstract: A circuit for inverting a number of n bits of a finite field of 2.sup.n =N+1 elements comprises a first circuit for raising to the power t=2.sup.n/2 receiving the number to invert. A first complete multiplier receives the number to invert and the output of the circuit for raising to the power t. A second circuit provides the product of the output of the circuit for raising to the power t and the inverse of the output of the first complete multiplier.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jacques Meyer
  • Patent number: 5610860
    Abstract: An integrated circuit memory comprises a circuit that keeps the column voltage constant during the recording of a binary value. This circuit has a differential amplifier which measures the difference between a reference voltage given by a voltage divider and a voltage representative of the bit line. This amplifier gives a signal that is applied to the gate of a transistor of the column-addressing circuit.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: March 11, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Olivier Rouy
  • Patent number: 5592115
    Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 7, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Christian G. Kassapian
  • Patent number: 5592428
    Abstract: A dynamic memory includes a plurality of cells including capacitors connected by columns to bit lines and by rows to selection lines. An even row and an odd row contain reference cells, the cells of the other rows being memory cells. The capacitors of the reference cells have the same value as the capacitors of the memory cells. Means are also provided for, prior to reading a memory cell of an even row, connecting the selection line of the odd row of reference cells to an element having the same capacitance as a selection line, but which is precharged at the state opposite to the state of the selection line of the odd row of the reference cells.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: January 7, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Michel Harrand, Michel Runtz
  • Patent number: 5589793
    Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.
    Type: Grant
    Filed: September 29, 1993
    Date of Patent: December 31, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Christian G. Kassapian
  • Patent number: 5587946
    Abstract: To reduce read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. The threshold voltage of nonselected cells (i.e., the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to a "body effect", whereby the threshold voltage depends on the voltage drop between the source terminal and the substrate. The source line of a selected cell is biased to a positive value greater than that of the bit line of the selected cell. Methods for reading, writing and erasing cells using certain voltage levels are disclosed.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: December 24, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Giovanni Campardo, Giuseppe Crisenza, Marco Dallabora
  • Patent number: 5581095
    Abstract: A bidirectional Shockley diode includes an N-type layer sandwiched between two P-type layers. A first N-type region in the P-type region extends over substantially one half of the upper surface. A second N-type region extends in the P-type layer substantially over one half of the lower surface. Each first and second region protrudes with respect to the median plane of the component by a length r such that ratio r/e is smaller than 0.5, e being the thickness of the component.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: December 3, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jean-Claude Salbreux
  • Patent number: D492692
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: July 6, 2004
    Assignee: American Power Conversion Corporation
    Inventors: Ray Fallon, Noel Fegan, Jacqueline Hayes, Eddie Grogan, David Mathieson
  • Patent number: RE35434
    Abstract: An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the out puts of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: January 28, 1997
    Assignee: SGS-Thomson Microelectronics S. r. l.
    Inventors: Alberto Gola, Angelo Alzati, Aldo Novelli
  • Patent number: RE35582
    Abstract: A method of lowering the power absorbed by an interface circuit, in the "power-down" state thereof, as incorporated to a telephone exchange and connected to a telephone subscriber line, being of a type which comprises a monitoring circuit portion connected between the line and the exchange. The method involves the steps of,detecting the polarization level of a conductor in the line,comparing that level with a reference value by means of a comparator having an input connected to the line and an output connected to the input of the monitoring circuit portion,switching the interface circuit to a standby state on a higher level than the reference value being sensed,once again detecting the polarization level of the line, this time through the interface circuit, andactivating the telephone exchange when, on completion of the second detection step, the polarization level stays above the reference value.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: August 12, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Angelo Pariani, Walter Rossi, Vanni Saviotti