Patents Represented by Attorney, Agent or Law Firm Bruce E. Hayden
  • Patent number: 6004027
    Abstract: A set of Unique Input/Output Sequence (UIO) Sets is identified for Finite State Machine (FSM) model (33) states. Each member of the Sets of UIO Sets is a UIO Set (63) which are sets of Input/Output (I/O) Sequences that each uniquely identifies FSM (33) states. FSM (33) state transitions are Edges-Under-Test (EUT). A Test Subsequence is constructed for each member of each UIO Set (63) selected for each EUT that includes the UIO Set member and the corresponding EUT. A Test Subsequence (TS) Graph (65) is constructed from the Test Subsequences by connecting Test Subsequence starting and ending states. A Verification Test Sequence for testing a Machine Under Test (14) for conformance with a FSM model (33) is constructed by touring the TS Graph (65).
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: December 21, 1999
    Assignee: Motorola Inc.
    Inventors: Xiao Sun, Carmie A. Hull
  • Patent number: 6006024
    Abstract: A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: December 21, 1999
    Assignee: Motorola, Inc.
    Inventors: Mohankumar Guruswamy, Daniel Wesley Dulitz, Andrea Fernandez, Srilata Raman, Robert L. Maziasz
  • Patent number: 5987086
    Abstract: A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: November 16, 1999
    Assignee: Motorola Inc.
    Inventors: Srilata Raman, Mohankumar Guruswamy, Daniel Wesley Dulitz, Venkata K. R. Chiluvuri, Robert L. Maziasz
  • Patent number: 5984510
    Abstract: A method for automatically synthesizing standard cell layouts(170) given a circuit netlist, a template describing the layout style and a set of process design rules (136) starts by numerating an ordered sequence of physical netlists from the logical netlist(138). Next, a netlist is selected from the ordered sequence of physical netlists (140). Components are placed according to the selected physical netlist (144). The components are routed to implement interconnections specified by the netlist (154). The components are compacted (156). A next netlist is selected from the ordered sequence of physical netlists. The steps of placing, routing and compacting the components are repeated. The layout with the smallest width is selected(166). Finally, ies, contacts and vias are added and notches filled (170) to improve yield and performance of the circuit.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: November 16, 1999
    Assignee: Motorola Inc.
    Inventors: Mohan Guruswamy, Daniel Wesley Dulitz, Robert L. Maziasz, Srilata Raman, Venkata K. R. Chiluvuri, Andrea Berens
  • Patent number: 5961622
    Abstract: A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: October 5, 1999
    Assignee: Motorola, Inc.
    Inventors: John Michael Hudson, Donald L. Tietjen, Terry L. Biggs
  • Patent number: 5960171
    Abstract: A compiled cycle based circuit simulator efficiently implements dynamic loop resolution at execution time. A static loop arises when a plurality of signals appear to be interdependent. In a properly designed circuit, apparent looping of signals is usually protected by other mutually exclusive signals. A dynamic loop exists when the signals are actually interdependent. A cyclic clock is divided into a fixed plurality of time slots. During each time slot that a plurality of interrelated signals can change, code for the interdependent signals used by other logic or memory elements are demand generated as function calls. Within each such called function, computation of dependent interdependent signals is by function call protected by control signals. Nondynamic static looping of signals is thus efficiently ignored. Dynamic looping is detected and reported through monitoring of function call depth.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: September 28, 1999
    Inventors: Alan Rotman, Eshel Haritan, Michael L. Braddock, Noam Erdman
  • Patent number: 5958635
    Abstract: Lithographic Proximity Correction (LPC) shapes are added (503) to a layer of a layout database file (501). Geometric criteria such as feature width are then used to filter the added LPC shapes (502). The LPC shapes are then modified (505) by determining which LPC shapes are within a predetermined distance from a shape in a layer of the second data base (504). The database file, including the modified LPC shapes, is then used to manufacture a set of lithographic masks (506). The lithographic masks are then used to pattern a set of wafers in the manufacture of integrated circuits (507).
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: September 28, 1999
    Assignee: Motorola, Inc.
    Inventors: Alfred John Reich, Hak-Lay Chuang, Michael E. Kling, Paul G. Y. Tsui, Kevin Lucas, James N. Conner
  • Patent number: 5951688
    Abstract: A data processor (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling an electrical interface configuration of the data processor. A set of bits (DA) in the control register (94) provides configuration control which indicates a pair of voltage level of data communicated with the data processor.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 14, 1999
    Assignee: Motorola, Inc.
    Inventors: William C. Moyer, Claude Moughanni
  • Patent number: 5920487
    Abstract: Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit design. When this is not the case, exposure energy such as light behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion, and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the circuit designs themselves can be altered so that the final printed results better matches the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Square (142), cross (162), octagon (172), and hammerhead (202) serifs are added to integrated circuit designs by shape manipulation functions to perform two dimensional (2-D) LPC.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: July 6, 1999
    Assignee: Motorola Inc.
    Inventors: Alfred J. Reich, Warren D. Grobman, Bernard J. Roman, Kevin D. Lucas, Clyde H. Browning, Michael E. Kling
  • Patent number: 5819062
    Abstract: A language is defined to describe design information that is readily available in electronic form. The syntax developed is applicable for use in the semiconductor industry, but other terms may be defined that are more appropriate for another use. Using the developed language, designers can describe their design intent in a spreadsheet as an input file. A neutral-format file generator reads this design information and translates the same into DXF output file, an industry standard neutral-file-format, which can be transferred into most CAD systems. All of the steps can be done electronically.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: October 6, 1998
    Assignee: Motorola Inc.
    Inventor: Ashok B. Srikantappa
  • Patent number: 5805774
    Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: September 8, 1998
    Assignee: Motorola, Inc.
    Inventors: J. Greg Viot, James M. Sibigtroth
  • Patent number: 5799143
    Abstract: A method for multiple context analysis of software applications in a multiprocessing (22, 23), multithreaded computer environment utilizes instrumentation code inserted (54, 55) into the applications. For each execution (67) of the application (60), a context set is selected (62). Execution of the instrumented code (67) provides information for analysis in an instrumentation buffer (82) addressed by a reserved register (80) or buffer pointer. The operating system is responsible for providing in the reserved register (80) the address of the instrumentation buffer (82) appropriate for each instrumented context executed. When the application (60) is done with an instrumentation buffer (82), the buffer may be processed by filter software (68).
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: August 25, 1998
    Assignee: Motorola, Inc.
    Inventors: Farooq Butt, Roger Smith, Katherine E. Stewart
  • Patent number: 5768170
    Abstract: A method and apparatus for efficiently generating multiple integer quotients of integer numerators divided by a common integer denominator are implemented by multiplying a floating point approximation of the reciprocal of the integer denominator by floating point representations of the numerators, biasing the floating point quotients before rounding up or down as required. First, an initial approximation of the reciprocal of the denominator is computed (102) by squaring (114) a limited precision square root of the reciprocal (112). A final reciprocal is computed using a finite power series (104). Finally, modified numerators are formed (106) by biasing the original numerators, products of the modified numerators multiplied times the reciprocal are computed, and the products are rounded up or down as required (108).
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: June 16, 1998
    Assignee: Motorola Inc.
    Inventor: Roger A. Smith
  • Patent number: 5761215
    Abstract: Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: June 2, 1998
    Assignee: Motorola, Inc.
    Inventors: Daniel M. McCarthy, Paul W. Hollis, Ruey J. Yu, Renny L. Eisele
  • Patent number: 5751593
    Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409).
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: May 12, 1998
    Assignee: Motorola, Inc.
    Inventors: Satyamurthy Pullela, Abhijit Dharchoudhury, David T. Blaauw, Tim J. Edwards, Joseph W. Norton
  • Patent number: 5740469
    Abstract: An apparatus for allowing a single software Tool (136) to read and write multiple Object File Formats utilize dynamically configurable and loadable Object File Readers (131) and Writers (139). A separate Reader (131) and Writer (139) can be implemented for each different Object File Format and variations thereof. Tools (136) communicate with the Readers (131) and Writers (139) using a Generalized Object File Program Interface (124). This Interface (124) utilizes Data Structures implementing a Generalized Object File Internal Representation (122) and an Applications Programmers Interface (120).
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: April 14, 1998
    Assignee: Motorola Inc.
    Inventors: Weiping Yin, Paul Hancock, Alan Weiner
  • Patent number: 5740199
    Abstract: A communication system (5) provides an improved wired-OR connection for use in the bidirectional communication of information between two devices. A first device is a master host device (10) which initiates all communications while one or more slave devices (40) connected to a wired-OR common communication line either receive information from or send information to the master device. Depending on a direction of a data transfer operation, either the master or the host determines a bit time required to perform the data transfer. Furthermore, a device which terminates the bit time is the device which issues a speed up pulse for driving the common communication line to a logic one value. Such speed up pulses permit faster communication than is normally possible on a wired-OR communication line and makes high speed bidirectional communication over a single wired-OR line practical.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: April 14, 1998
    Assignee: Motorola Inc.
    Inventor: James M. Sibigtroth
  • Patent number: 5726944
    Abstract: An SRAM memory cell (10) is provided a boosted voltage by a charge pump (56) to reduce the soft error rate within the SRAM (10) and to improve bit cell stability. A voltage regulator (58) is coupled to the charge pump (56) to regulate the operation of the charge pump (56) and its outputted boosted voltage. The voltage regulator (58) regulates the boosted voltage over three operating states: low supply voltage, steady state operation, and burn-in.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: March 10, 1998
    Assignee: Motorola, Inc.
    Inventors: Perry H. Pelley, III, Robert C. Taft
  • Patent number: 5721509
    Abstract: A charge pump (40) is implemented with several stages (30), including a control stage (50), in a manner integral with a ring-oscillator loop. The charge pump (40) is more efficient for producing voltage VBB to supply to a substrate well implementing circuitry such as a DRAM or SRAM (61), since there are no threshold voltage drops across any of the critical path transistors (M3) within the charge pump (40). This is accomplished by providing a boosted signal level from the proceeding stage (30). In the design, parasitic diode leakage is negligible.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: February 24, 1998
    Assignee: Motorola, Inc.
    Inventors: Robert C. Taft, Perry H. Pelley, III
  • Patent number: 5721726
    Abstract: Output on Multiple Time Division Multiplexer (TDM) HDLC lines (28) is selectively and gracefully throttled. A throttling signal (99) is asserted whenever either the output FIFO queue (58) is almost full or the input FIFO queue (56) is almost empty. Whenever an in frame/out of frame state transition occurs for a given logical channel, a check is made whether throttling is required (292, 296). If throttling is required, an HDLC flag byte is transmitted (291, 299), delaying all such state transitions until the throttling signal (99) is no longer asserted.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: February 24, 1998
    Assignee: Motorola, Inc.
    Inventors: Moti Kurnick, Boaz Shachar, Udi Barel