Abstract: A memory that stores a plurality of data storage words, each data storage word includes a plurality of data storage cells arranged as a plurality of columns of data storage cells, at least one of the data storage cells storing data specifying a data value having 3 or more states. The memory includes a plurality of data lines, one such data line corresponding to each column of data storage cells. Each data storage cell sets its state or provides a signal representative of its state via the data line connected to that cell in response to control signals. The memory also includes an error encryption circuit for receiving a data word to be stored in the memory and generating therefrom an encrypted data storage word. The encryption circuit divides the encrypted data storage word into a plurality of sub-data storage words.

Abstract: A current confinement element that can be used in constructing light-emitting devices. The current confinement element includes a top layer and an aperture-defining layer. The top layer includes a top semiconducting material of a first conductivity type that is transparent to light. The aperture-defining layer includes an aperture region and a confinement region. The aperture region includes an aperture semiconducting material of the first conductivity type that is transparent to light. The confinement region surrounds the aperture region and includes a material that has been doped to provide a high resistance to the flow of current. In one embodiment of the invention, the confinement region includes a semiconducting material of a second conductivity type.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: A laser diode that includes a light guiding structure that improves the light-output-versus-current curve by altering the multiple spatial modes of the laser diode. A laser diode according to the present invention includes a bottom mirror constructed on an electrically conducting material, an active region constructed from a first conductive spacer situated above the bottom mirror, a light emitting layer, and a second conductive spacer situated above the light emitting layer. The laser diode also includes a top mirror constructed from a plurality of mirror layers of a semiconducting material of a first conductivity type that are located above the second conductive spacer. The adjacent mirror layers have different indexes of refraction. One or more of the top mirror layers is altered to provide an aperture defining layer that includes an aperture region that alters the spatial modes of the device.

Abstract: A current confinement element that can be used in constructing light-emitting devices. The current confinement element includes a top layer and an aperture-defining layer. The top layer includes a top semiconducting material of a first conductivity type that is transparent to light. The aperture-defining layer includes an aperture region and a confinement region. The aperture region includes an aperture semiconducting material of the first conductivity type that is transparent to light. The confinement region surrounds the aperture region and includes a material that has been doped to provide a high resistance to the flow of current. The aperture-defining layer is constructed by implanting or diffusing elements into one or more of the mirror layers prior to depositing the remaining mirror layers on top of the aperture-defining layer.

Abstract: A memory having a two-dimensional array of memory cells organized as a plurality of rows and columns. The memory includes spare rows and columns. A controller in the memory tests the memory at power up and determines if any of the rows or columns are defective. A defective row or column is re-mapped to one of the spare rows or columns, respectively. Data specifying the re-mapping is stored in a separate re-mapping address decode circuit. When an address specifying a memory cell is received by the memory, a conventional address decode circuit decodes the address at the same time the re-mapping decoder searches for a match to the address. If the re-mapping decoder finds the address, it inhibits the conventional decoder and supplies the appropriate column or row select signals. The re-mapping decoder is preferably constructed from a content-addressable memory.

Abstract: A method of operating a computer to generate an object class definition from a procedural program having a main program and a plurality of procedures. The invention determines a set of procedures, including at least one procedure that is actually called by the procedural program during the execution of the main program thereof. The resulting object definition has a main method or procedure that reproduces the behavior exhibited by the procedural program when the main method is invoked or the main procedure is executed. In addition, the invention generates a method in the object class definition corresponding each procedure in the procedural program that is actually used in the procedural program.

Abstract: A method for operating a data processing system to control a device under test and to collect data from that device. The user is provided with a first display having a list of elementary tasks having first and second tasks from which a user selects one or more elementary tasks. The first task applies a signal to the device under test when that task is executed and the second task causes the data processing system to receive data from the device under test. The user edits task parameters using a second display to provide a current test definition. In response to user input, the data processing system executes each of the tasks in the current test definition and stores any data received from the device under test in a data set that includes the current test definition and which is displayed in a third display.

Abstract: A printing composition constructed from a printing layer and a blotting layer. The printing layer has a plurality of pores connecting the top and bottom surfaces thereof and is adapted for accepting ink that is retained in the pores. The blotting layer has a top surface that is in contact with the bottom surface of the printing layer. The blotting layer is constructed from a material that has an affinity for the ink that is less than that required to remove the ink from the pores if the pores are not filled with the ink. The printing layer may be constructed from a plastic that has been coated with a surfactant that renders the sides of the pores hydrophilic. The blotting layer may be constructed from a sheet of plastic having pores therein. The blotting layer may also be constructed from a sheet of paper. In the preferred embodiment of the present invention, the printing layer is an electret.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address.

Abstract: An imaging element and an imaging array constructed from such elements. The preferred imaging element is constructed from a photodiode having a parasitic capacitance Cpd; and an amplifier for measuring the charge stored on the parasitic capacitor. The amplifier includes an opamp having a signal input, reference input and output; the first terminal of the parasitic capacitor is connected to the signal input. The imaging element includes a reset switch for shorting the signal input and the output of the opamp, and capacitive network. The capacitive network connects the signal input and the output of the opamp, and provides a capacitance of CT between the signal input and the output of the opamp wherein CT<Cpd. The capacitive network is constructed from a plurality of component capacitors. Preferably each component capacitor has a capacitance greater than or equal to Cpd. An imaging array according to the invention includes a plurality of imaging elements, a signal bus, a reset bus, and a reset circuit.

Abstract: A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO2 or Si3N4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond, the bottom electrode to the substrate surface.

Abstract: Bandlimiting and capacitive feedback is used to reduce pixel reset noise in an image sensor without adding lag. An image sensor includes a reset circuit having a reset control loop for controlling pixel reset. The reset control loop includes, for example, a reset amplifier and a transistor. The reset amplifier has a first input coupled to a reset voltage and a second input coupled to a readout node (e.g., the source of a NMOS transistor). When the reset voltage exceeds the readout node voltage, the reset amplifier output voltage rises and turns on the transistor. The output voltage of the transistor then follows the reset voltage until the reset voltage stops rising and the readout node voltage overshoots the reset voltage. After the readout node voltage overshoots the reset voltage, the reset amplifier output voltage drops and turns the transistor off. With the transistor off, only the overlap capacitance of the transistor is used to control the reset control loop[.

Abstract: A method for constructing an electrode on a silicon substrate in which the electrode will be subjected to high temperatures during subsequent processing steps. A titanium oxide layer is deposited on the silicon substrate and annealed at a temperature higher than any subsequent temperature to which the titanium oxide layer will be subjected. The electrode is then deposited on the titanium oxide layer. The electrode is preferably platinum or a titanium/platinum composition. The platinum is also annealed to a temperature higher than any subsequent temperature to which the electrode will be subjected. In the preferred embodiment of the present invention, the electrode is constructed in a trench that is etched in a layer of metallic titanium that is deposited over the titanium oxide layer.

Abstract: A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column.

Abstract: A memory that includes a plurality of storage blocks. Each block has a plurality of storage cells constructed from a storage element and an isolation transistor. The storage cells in a block are organized as a plurality of rows and column units. Each column unit includes a first bit line and a plurality of the memory cells connected to the first bit line by the isolation transistors in those memory cells. The memory also includes a first multiplexer connected to a plurality of the first bit lines in a first one of the memory blocks, the first multiplexer connecting one of the first bit lines to a first conductor in response to one or more first multiplexer control signals. The first multiplexer is located adjacent to the storage block containing first bit lines connected thereto. The first conductor is connected to a sense amplifier for reading the contents of the storage cells. The sense amplifier may be located adjacent to the first multiplexer or at a remote location relative to the storage block.

Abstract: A multi-level memory in which each storage cell stores multiple bits. The memory includes a plurality of storage words, a data line, a plurality of reference lines, and a read circuit. Each storage word includes a data memory cell and a plurality of reference memory cells. A stored charge determines a conductivity value measurable between the first and second terminals of each memory cell. The read circuit generates a digital value indicative of the value stored in the data memory cell of a storage word that is connected to the data and reference lines by comparing the conductivity of the data line with a continuous conductivity curve determined by the conductivities of the reference lines.

Abstract: An amplifier for measuring the charge stored on a source capacitor having a capacitance Cpd. The amplifier includes an opamp having a signal input, reference input and output; the first terminal of the source capacitor is connected to the signal input. The amplifier includes a reset switch for shorting the signal input and the output of the opamp, and a capacitive network. The capacitive network connects the signal input and the output of the opamp, and provides a capacitance of CT between the signal input and the output of the opamp wherein CT<Cpd. The capacitive network is constructed from a plurality of component capacitors. Preferably each component capacitor has a capacitance greater than or equal to Cpd. In one embodiment of the invention, the capacitive network includes first, second, and third component capacitors, each capacitor having first and second terminals.

Abstract: A variable conductance device having a first source region and a first drain region in a semiconductor substrate. A first channel region connects the first source and the first drain regions. A first resistive layer overlies the first channel region and has first and second electrical contacts spaced apart from one another thereon. The conductance of the path between the first source region and the first drain region depends on the current flowing between the first and second electrical contacts. By adding a FET having its gate and source shorted together to the variable conductance device, a device having the current gain characteristics of a bipolar transistor is obtained. The first drain region is connected to the drain of the FET and the source of the FET is connected to the second electrical contact. The precise form of the current transfer function can be altered by connecting a number of variable conductance devices according to the present invention in parallel.

Abstract: A printing composition that is adapted for printing on computer printers and the like. The printing composition includes a backing sheet and a printing sheet. The printing sheet includes an electret which is reversibly bound to the backing sheet. In one embodiment of the invention, the printing sheet is coated with an ink absorbing coating. The electret can be constructed from materials such as polypropylene or polyethylene that have been subjected to electrostatic fields.