Abstract: An apparatus and method of implementing a circuit representing a complex polynomial equation in a hardware description language (HDL) for implementing an ASIC (Application Specific Integrated Circuit) is provided. A serial circuit representing the complex polynomial equation is implemented in a software program. The serial circuit implementation is simulated to produce a plurality of parallel equations that are mapped into HDL with ASCII strings. In one embodiment, the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry.

Abstract: An apparatus and method for a communications network including at least one interface circuit reads frame data received from the communications network and writes frame data to be transmitted over the communications network, the frame data including a plurality of transport overhead fields. The apparatus includes signature logic coupled to the interface circuit, the signature logic identifying signature data and writing the signature data into transport overhead fields in an outgoing frame. Reflector logic coupled to the interface circuit copies data from one of the received transport overhead fields, the copied data being placed into a transport overhead field in the outgoing frame, the copied data including the received signature data. The interface circuit compares the copied data to earlier received frame data from the communications network, the determination of a mismatch identifying a transition requiring an update of at least one routing table.

Abstract: Disclosed is a method and apparatus for synchronizing data. In one embodiment, the apparatus includes a first communication link for transmitting first data and a second communication link for transmitting second data. A circuit coupled to the first and second communication links. The circuit is configured to receive the first and second data. The circuit is configured to synchronously output the first and second data when the first and second data are received by the circuit out of synchronization.

Abstract: A method and apparatus for an integrated process modeler is described. The modeler comprises a non-technical interface to permit design of a business process by a non-technical use and a technical interface to implement substeps of the process to automate technical aspects of the process by a technical user, using the same process modeler. The resulting process designed to be used by non-technical employees, to automatically lead the non-technical employees through the business process.

Abstract: Two computers of a standard size, such as 1U, are mounted in a single standard size space. This arrangement almost doubles the space utilization of a rack and thereby halves the cost of hosting a dynamic computing environment. Also, a plurality of chassis are mounted on a rack where each chassis can hold more than one single-board computers. This arrangement enables provisioning of computing environments computing power in increments other than multiples of 1U.

Abstract: In a butterfly network, a number of switches are set to provide two paths that are independent of each other, from a first switch to a second switch, and from the first switch to a third switch respectively. Identification of switches to be set from among all switches in the butterfly network depends on the locations of the first switch, the second switch and the third switch relative to one another. The to-be-set switches are determined by starting with the first switch as a preceding switch, identifying the next switch for a path by simply changing the level number (e.g. incrementing the level number) of a preceding switch in the path, and by changing a bit of the row number of the preceding switch (e.g. by replacing the ?-th bit with a corresponding bit from the destination switch's row number), and repeating such acts with the just-identified switch as a preceding switch. The direction of the path is reversed on reaching a last level or a last row of the network.

Abstract: A delay measurement technique according to an embodiment according to the present invention is based on the precept, ascertained by the inventors, that a link between network nodes will often contribute to the delay encountered between several different pairs of network nodes. Such a technique identifies the path between each pair of nodes by a list of links that form the path. Paths that are orthogonal are treated as being necessary for describing the delays encountered between nodes, and, once the requisite set of orthogonal paths has been derived, all other paths can be described in terms of one or more of these orthogonal paths. Such a technique also lends itself to matrix representation of the paths, and the use of matrix manipulation techniques in deriving delay and jitter.

Abstract: The development port or Debug port of a microprocessor on an intelligent daughterboard is used for downloading code or configuration information from a motherboard for use in boot-up. In various aspects, the code or configuration information can include information used for configuring a port, other than the development port, and/or for configuring a memory controller, such as for a daughterboard DRAM. Use of the Debug port makes it possible to reduce or eliminate the need for storing boot-up code or configuration information on a daughterboard ROM, or other non-volatile memory, thus reducing cost and space requirements, power consumption and the like.

Abstract: An application archive is searched for an existing translation for a text string in an application to be localized. The text string is associated with context information that identifies a location of the text string in the application. If an existing translation is found that matches the text string, and all, or alternately part of, the context information, the existing translation is logically linked to the text string. In one aspect, the existing translation is selected from multiple matches based on number of occurrences. In another aspect, the existing translation is submitted to a manual validation process.

Abstract: A source synchronous clocking synchronizes data and clock signals transmitted between an ATM layer and a link layer. The source synchronous clocking includes a source clock domain in a first layer which includes a register having a first input for receiving a data signal, a second input for receiving a clock signal, and an output; and a buffer having an input for receiving the clock signal and an output, the buffer generating a delay that is substantially equivalent to a delay through the register. The source synchronous clocking further includes a destination clock domain in a second layer which includes a register having a first input and a second input, the first input of the register of the destination clock domain being coupled to the output of the register in the source clock domain.

Abstract: A web page processing system that processes users requests using predefined, flexible templates and corresponding logic. Main processing handles non-departmental specific functions such as security and data decoding and encoding. Data decoding and encoding includes converting data to a universal character coding representation. The system also includes software for determining the character set used by a user for converting universal character coded data into a particular language code. The system includes a secure private protocol for advantageously securing the system in addition to traditional router based firewall technology. Links to departmental level functions through template files are provided for department specific functions and processing of department related information received by the system. In addition, web page customization is provided by specialized links to external web sites containing logos and other indicia to be included on returned web pages.

Abstract: A method and apparatus to build a migration package. According to one embodiment of the invention, a plurality of programming elements are developed and stored in a configuration repository. The configuration repository also includes metadata used to describe each of the programming elements. Selected programming elements are placed in a set of one or more migration scripts to be stored in the migration package. The set of migration scripts may include a master configuration file and a driver file.

Abstract: A method and system for exposing a version-independent interface to a computer resource. The interface system exposes a version-independent interface to a computer resource, such as a database or computer program. The interface system also provides a version-dependent interface to the computer resource that is typically not exposed. When the computer resource is modified, the version-dependent interface may be modified, but the version-independent interface might not be modified. When the version-dependent interface is modified, a mapping is generated (in some cases automatically) between the version-independent interface and the version-dependent interface. When an accessing computer program uses the version-independent interface to request services of the computer resource, the system uses the mapping to map the request to a request that is appropriate for the version-dependent interface.

Abstract: The present invention relates to a method and apparatus for balancing loads in multiple switching fabrics. Each switching fabric comprises data ports through which data frames enter or exit the switching fabric. In one embodiment, the apparatus includes a buffer and a routing data generation circuit. The buffer receives a data frame to be transmitted to a destination device via one of the switching fabrics coupled thereto. The routing data generation circuit is coupled to the buffer. The routing data generation circuit generates and adds routing data to the data frame received by the buffer. The routing data identifies one of the data ports of one of the switching fabrics through which the data frame will exit to reach the destination device. After the routing data is added to the data frame, the buffer transmits the data frame to one of the switching system.

Abstract: Methods and articles of manufacture for integrated, automatic pseudo localization of software applications are disclosed herein. A pseudo localization process, comprised of one or more utility applications, is integrated into a build cycle for a developing software application to generate pseudo-translated user-interface code as part of a build process. A build application may then generate a pseudo-language build of the developing software application and/or development database to enable testing and identification of internationalization defects that would prevent effective localization of the software product for the international market.

Abstract: A system, apparatus, and method for routing work items to agents, wherein the work items can be of one of two or more different communication media types from one of two or more different communication channels. A queuing engine includes a list of routes and each route is associated with one or more properties. The list of routes can further include information related to one or more escalation rules for each route; the type of communication media available along the route for handling one or more of the work items; whether the route is active; the priority of the route; whether work items can be handled real-time; the service level for work items handled on the route; and the number of work items that can be assigned to the route.

Abstract: A method, system, computer system and computer program product to maintain consistency between mirrored copies of data. A first data change map identifies regions that are about to be updated. If a system failure occurs during the update, the first data change map identifies regions that were being changed so that only those regions can be synchronized to restore consistency between the mirrored copies of data. A second data change map tracks changes made to data after a snapshot of the mirrored data is taken. This second data change map enables the mirrored copies of data to be synchronized without copying all data from one mirrored copy to another. The first and second data change maps are updated in parallel to reduce processing time and overhead. This parallel processing enables fast restoration and synchronization of mirrored copies of data, while having minimal effect on performance of applications using the data.

Abstract: Disclosed is an apparatus or method performed by a computer system for creating a hierarchy of data volumes. Each data volume in the hierarchy is a point-in-time (PIT) copy of another data volume in the hierarchy or a PIT copy of a data volume V. In one embodiment of the apparatus or method, the contents of a first data volume in the hierarchy can be refreshed to the contents of a second data volume in the hierarchy such that the first data volume becomes a PIT copy of the second data volume. Before the first data volume is fully refreshed to the contents of the second data volume, data of the first data volume can be read or modified.

Abstract: In a system in which read data tracking and caching is used to recover from data corruption, a first request to read data from a primary data mirror is received from a computer system. Data is read from the primary data mirror in response to receiving the first request. Additionally data from a mirrored copy of the primary data mirror is read. Data read from the primary data mirror is returned to the computer system. Data read from the mirrored copy is stored into a memory device. If a second request is received from the computer system to read the same data of the first request, data stored in the memory device may be returned in response thereto.

Abstract: A method, computer program product, computer system and system that enable symmetrical data change tracking with respect to a set of data and a copy of the set of data, referred to as a snapshot or a second set of data. The data and the copy may be independently updated after the two sides are “split.” A join may be performed of the two sides of the split to resynchronize the data. For the first set of data, an accumulator map tracks changes to the first set of data and a volume map tracks changes to the first set of data with respect to a second set of data. For the second set of data (the snapshot), a second accumulator map tracks changes to the second set of data and a second volume map tracks changes to the second set of data with respect to the first set of data.