Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).

Abstract: An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis.

Abstract: An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150) comprises an external clock source (152) and an internal clock source (177). A first multiplexer (164) is provided and has the external clock source (152) and the internal clock source (177) as data inputs and an internal clock selection bit value (B.sub.-- CLKMUXB 176) as a data select input. A second multiplexer (156) having the external clock (152) and the output of the first multiplexer as data inputs and a data select input (BCLK.sub.-- EN) based on whether a self-test mode is activated (BIST.sub.-- EN) and the internal clock selection bit value (B.sub.-- CLKMUXB) is also provided. The external clock source (152) or internal clock source (177) is selected based on the value of the internal clock selection bit value (B.sub.-- CLKMUXB 176) and whether the self test mode is activated (BIST.sub.-- EN).

Abstract: Built-In-Logic-Block-Observation registers BILBO are coupled to the output of a Control-Read-Only-Memory CROM in the write-state-machine of a flash EPROM. The Built-In-Logic-Block-Observation registers BILBO include master/slave latches M/SL, shadow latches SHL, and other logic circuitry that enable the various modes of operation required for pulse timing and for signature analysis. During operation a pre-defined FLASH command sequence requests a Control-Read-Only-Memory CROM signature analysis that executes a set of instructions causing the Built-In-Logic-Block-Observation registers BILBO to be placed in the Multiple-Input-Signature-Register Mode and that steps through the Control-Read-Only-Memory CROM until all valid addresses have been evaluated. The resultant Control-Read-Only-Memory CROM signature is then scanned out and verified. The invention eliminates the need for a separate stand-alone Linear-Feedback-Shift-Register LFSR used for pulse timing.

Abstract: A method of removing inorganic contamination (contamination 104 of FIGS. 2a-2b) from a layer (layer 102) overlying a substrate (substrate 100), the method comprising the steps of: removing the layer overlying the substrate with at least one removal agent; reacting the inorganic contamination with at least one conversion agent, thereby converting the inorganic contamination; removing the converted inorganic contamination by subjecting it to at least one solvent agent, the solvent agent included in a first supercritical fluid; and wherein the converted inorganic contamination is more highly soluble in the solvent agent than the inorganic contamination.

Abstract: A method of removing inorganic contamination from substantially the surface of a semiconductor substrate, the method comprising the steps of: reacting the inorganic contamination with at least one conversion agent, thereby converting the inorganic contamination; removing the converted inorganic contamination by subjecting it to at least one solvent agent, the solvent agent is included in a first supercritical fluid (preferably supercritical CO.sub.2); and wherein the converted inorganic contamination is more highly soluble in the solvent agent than the inorganic contamination.

Abstract: A resonant tunneling diode stack used as a memory cell stack (X0-Xn) with sequential read out of bits of data cells (X1-Xn) by increasing ramp rates to transfer the stored bit to a lowest ramp rate cell (X0).

Abstract: An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply.

Abstract: A virtual sensor based monitoring and fault detection/classification system (10) for semiconductor processing equipment (12) is provided. A plurality of equipment sensors (14) are each operable to measure a process condition and provide a signal representing the measured process condition. A plurality of filtering process units (16) are each operable to receive at least one signal from the plurality of equipment sensors (14) and to reduce data represented by the at least one signal and provide filtered data. A plurality of virtual sensors (24) are each operable to receive the filtered data. The plurality of virtual sensors (24) model states of the processing equipment (12) and a work piece in the processing equipment (12). Each virtual sensor is operable to provide an output signal representing an estimated value for the modeled state.

Abstract: A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.

Abstract: A HgCdTe S-I-S (semiconductor-insulator-semiconductor) two color infrared detector wherein the semiconductor regions are HgCdTe with different compositions for the desired spectral regions. The device is operated as a simple integrating MIS device with respect to one semiconductor. The structure can be grown by current MBE techniques and does not require any significant additional steps with regard to fabrication.

Abstract: Seismic data is combined with well log data to generate a two-dimensional geopressure prediction display; this permits deviated and horizontal well planning plus lithology detection. Shale fraction analysis, compaction trend, and seismic velocity may be automatically or interactively generated on a computer work station with graphics displays to avoid anomalous results. Corrections to velocity predictions by check shots or VSP, and translation of trend curves for laterally offset areas increases accuracy of the geopressure predictions. Multiple wells' logs in a basin permits analysis fluid migrations.

Abstract: The disclosure relates to a method of purifying cadmium and tellurium and forming pure, stoichiometric cadmium telluride therefrom as well as the apparatus for making such cadmium telluride. The cadmium and tellurium are purified by heating each separately to volatilization and passing water in a reducing gas through the volatilized cadmium and tellurium to react with impurities and form gases or precipitates. The cadmium and tellurium are volatilized at different predetermined temperatures such that the amount of each volatilized will be the same so that reaction later takes place with stoichiometric amounts of the elements to form the cadmium telluride. The cadmium telluride is then condensed at low enough temperature so that the remaining gases pass out of the system.

Abstract: A fiber optics input device receives a light beam from a movable light source relative to the input device for providing input signals to a terminal. The device includes a single plane of parallel, clad optical fibers forming columns of a matrix and another similar single plane forming rows, the two planes being placed together to form the matrix. The cladding is removed from the top surface of each fiber to form a window therein to permit the light beam to directly contact the selected window in the column plane and to permit the light beam that passes the column plane optical fibers to enter the window of the row plane. Light sensors are connected to the ends of the optical fibers in both the column and row planes so that a first signal is generated indicating a column position and a second signal is generated indicating a row position, thereby fixing the intersection of the column and row optical fibers at the point where the light beam impinges.

Abstract: A lift-off method for forming regions of a first semiconductor such as GaAs (104) in recesses in a substrate of a second semiconductor such as silicon (102) with the surface of the first semiconductor region (104) coplanar with the surface of the second semiconductor layer (102). Also, interconnected devices in both regions. Preferred embodiment methods include growth by molecular beam epitaxy of a layer of the first semiconductor on a masked and recessed substrate of the second semiconductor followed by photolithographic removal of the grown layer outside of a neighborhood of the recesses and lift-off (by mask etching) of the remainder of the grown layer outside of the recesses.