Abstract: A method of image/video compression with intra-coding blocks analyzed for sum of absolute magnitudes of AC coefficients of DCT of block to determine whether to approximate the block with 0 AC coefficients, and with inter-coding blocks analyzed for sum of absolute differences of block and predicted block to determine whether to approximate the block with a 0 block.

Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability figure (logarithm of ratio of maximum survivor path metric minus minimum survivor path metric divided by 0 state path metric minus minimum survivor path metric) with a small lookup table plus simple logic.

Abstract: A high speed Bluetooth system with switch-to quadrature amplitude modulation allows for simple mobile devices with video data rates in applications such as Internet downloading. Mobile devices may have multiple antennas and adaptive hopping frequencies.

Abstract: Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of frames. Phase alignment for a parametric coder aligns synthesized speech frames with adjacent waveform coder synthesized frames. Zero phase alignment of speech prior to waveform coding aligns synthesized speech frames of a waveform coder with frames synthesized with a parametric coder. Inter-frame interpolation of LP coefficients suppresses artifacts in resultant synthesized speech frames.

Abstract: Efficient reconstruction of a discrete signal in a range from subband coefficients of multirate analysis filtering translates the range into required input coefficient ranges and minimizes computation and memory access.

Abstract: Spreading factor (SF) estimation in a code division multiple access (CDMA) spread spectrum system where the SF of the data channel may change on a frame-by-frame basis to reflect a change in the data rate for each corresponding frame. The SF estimation methods despread the data channel for all possible SF values, perform maximal ratio combining (MRC) when resolved multipaths occur, take the absolute value of the MRC results, and average these absolute values over many symbol periods to obtain decision statistics for the various SF's. The SF estimation methods then post-process these decision statistics and make a SF decision.

Abstract: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

Abstract: MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations. The cascade architecture limits the required number of max* blocks which compute the logarithm of a sum of exponentials as part of the BCJR method.

Abstract: Digital Still Camera (DSC) includes separate preview engine, burst mode compression/decompression engine, image pipeline, CCD plus CCD controller, and memory plus memory controller. ARM microprocessor and DSP share control. Color filter array interpolation by use of green high-frequency added to red and blue plus interpolation.

Abstract: Turbo encoder with even-odd bit interleaving for upper and lower component convolutional encoders and symbol-level interleaving after mapping to modulation symbols plus symbol-level buffer for both ARQ and Turbo decoding.

Abstract: Power transient control in an optical network by power measurement and prediction with a simple-to-compute model to drive an optical filter control.

Abstract: A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).

Abstract: A fast Fourier transform with sequential memory accessing within each stage.

Abstract: A method of decoding variable length codes converts a variable length code table into standard format decomposition tables from which a universal variable length decoder can decode. This allows the same universal variable length decoder to decode any variable length code. The memory required to store the standard format decomposition tables is minimized by the conversion process.

Abstract: A method of image encoding using subband decomposition followed by modified zerotree coding with a symbols for zero and significant zerotrees and isolated zeroes and isolated significant coefficients.

Abstract: The digital communications receiver receives an analog signal, modulated with digital information. The receiver converts the analogue signal to a digital signal, and demodulates the digital signal to recover the complex valued components of the transmitted digital signal. The complex valued components are low pass filtered and passed through an adaptive pre-equalizer filter, to reduce eigen value spread. The filtered complex valued signal is then subject to a decision feedback equalization, which operates using a series of adaptive filters additionally to remove artifacts of inter-symbol interference. The resulting filtered and equalized complex valued signal is the converted to a digital signal to recover the digital information.

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Abstract: An interpolation for a Bayer pattern color-filtered array with edge enhancement by clamping green interpolation values.

Abstract: The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.