Patents Represented by Attorney, Agent or Law Firm Carol W. Burton
  • Patent number: 6804131
    Abstract: The present invention relates a Pulse Width Modulation (PWM)/linear driver for an electromagnetic load by a bridge circuit of the type having a signal input and a signal output and at least two conduction control inputs for driving a voice coil motor in a linear mode and in a pulse width modulation. The bridge circuit is driven by a PWM converter coupled to one of said two control inputs and by a linear amplifier coupled to the other of said two control inputs.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: October 12, 2004
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ezio Galbiati, Michele Boscolo
  • Patent number: 6804245
    Abstract: A central route table design in a fiber channel switch for providing one location for D_ID and exit port combinations. The fiber channel switch has a plurality of ports, each are coupled to the central route look-up table.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: October 12, 2004
    Assignee: McData Corporation
    Inventors: William J. Mitchem, Jeffrey J. Nelson
  • Patent number: 6664974
    Abstract: A method for automatically determining whether a browser supports scalable vector graphics (“SVG”). The method uses a two prong process to make a proper detection for various types of browsers. The method includes using JavaScript to detect Multipurpose Internet Mail Extensions (“MIME”) types from the browser to detect SVG support. If scanning of the MIME types detects that SVG support is present, the requested web page containing SVG content is sent. If no SVG support is detected, the non-SVG version of the web page is sent to the browser. If the browser does not return a list of MIME types, the method of Visual Basic Scripting Edition language (“VBScript”) to instruct the browser to create an SVG object on the client device. If the object is created, SVG support has been detected, and the browser is served the web page having SVG content.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: December 16, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Ana M. Lindstrom-Tamer
  • Patent number: 6416936
    Abstract: A top surface imaging technique for top pole tip width control in a magnetoresistive (“MR”) or giant magnetoresistive (“GMR”) read/write head is disclosed in which a multi-layer structure is employed to define the thick photoresist during processing resulting in much improved dimensional control. To this end, a relatively thin upper photoresist layer is patterned with much improved resolution, an intermediate metal or ceramic layer is then defined utilizing the upper photoresist layer as a reactive ion etching (“RIE”) mask, with the intermediate layer then being used as an etching mask to define the bottom-most thick photoresist layer in a second RIE process. As a consequence, a much improved sub-micron pole tip width along with a high aspect ratio and vertical profile is provided together with much improved critical dimension control.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: July 9, 2002
    Assignee: Matsushita-Kotobuki Electronics, Industries, Ltd.
    Inventors: Michael J. Jennison, Wei Pan
  • Patent number: 6377186
    Abstract: A sensor for determining the position of a movable object along a selected axis. The system includes a target positioned at a location aligned with the selected axis. An optical energy emitter is mounted on the movable object and has a beam dispersion greater than two degrees directed at the target. An optical energy receiver is mounted on the movable object and aligned to receive optical energy reflected by the target. The optical energy detector generates a receive signal indicating reception of the optical energy. A time of flight circuit coupled to the emitter and receiver generates a flight time signal indicating the elapsed time from emission of the optical energy to reception of reflected optical energy. A control circuit monitors the flight time signal and outputs a position signal indicating position of the movable object with respect to the target.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: April 23, 2002
    Assignee: Laser Technology, Inc.
    Inventors: Jeremy G. Dunne, Patrick J. Delohery
  • Patent number: 6376259
    Abstract: A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: April 23, 2002
    Assignee: Ramtron International Corporation
    Inventors: Fan Chu, Glen Fox
  • Patent number: 6339468
    Abstract: Disclosed is an optical sensor used for remote laser level monitoring in liquid storage vessels. The sensor is mounted directly to a standard tank nipple, located on top of the vessel, by a threaded connecting means and is linked to a laser measurement device via fiber optic cabling. The level in the vessel is measured as a function of the time required for a laser signal to be transmitted from the sensor, reflected off the liquid surface and returned to the receiver lens located in the sensor.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: January 15, 2002
    Assignee: Laser Technology, Inc.
    Inventors: Bruce Clifford, John Harrison
  • Patent number: 6301183
    Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: October 9, 2001
    Assignee: Enhanced Memory Systems, Inc.
    Inventors: David Bondurant, David Fisch, Bruce Grieshaber, Kenneth Mobley, Michael Peters
  • Patent number: 6287637
    Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: September 11, 2001
    Assignee: Ramtron International Corporation
    Inventors: Fan Chu, Glen Fox, Brian Eastep
  • Patent number: 6279564
    Abstract: An apparatus for cutting a substantially cylindrical work piece in a direction generally perpendicular to a longitudinal axis of the work piece includes a wire having a plurality of cutting elements affixed thereto and a wire drive mechanism for driving the wire across and through the work piece. The wire drive mechanism includes a capstan to move the wire orthogonally across a longitudinal axis of the work piece, a rotational drive to oscillate the wire around the longitudinal axis and an advancing drive to advance the wire perpendicularly through the longitudinal axis of the work piece. In a particular embodiment disclosed herein, the apparatus comprises imparts a substantially rocking motion to the wire drive mechanism about the longitudinal axis of the work piece and the cutting elements of the wire are impregnated diamonds.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: August 28, 2001
    Inventors: John B. Hodsden, Steven M. Luedders
  • Patent number: 6252793
    Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: June 26, 2001
    Assignee: Ramtron International Corporation
    Inventors: Judith E. Allen, William F. Kraus, Lark E. Lehman, Dennis R. Wilson
  • Patent number: 6249014
    Abstract: A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si3N4 itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a “short term” hydrogen barrier.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: June 19, 2001
    Assignee: Ramtron International Corporation
    Inventor: Richard A. Bailey
  • Patent number: 6242299
    Abstract: A continuous barrier layer is formed after a local interconnect metal layer is formed between the top electrode of a ferroelectric capacitor and the source/drain contact of a memory cell transistor in an integrated ferroelectric memory. After contact has been made to the top electrode of the ferroelectric capacitor, a thin dielectric layer is deposited using a material that provides an effective hydrogen barrier to the ferroelectric capacitor. The barrier layer minimizes damage to the ferroelectric capacitor and thus improves electrical performance.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: June 5, 2001
    Assignee: Ramtron International Corporation
    Inventor: George Hickert
  • Patent number: 6238933
    Abstract: Ferroelectric switching properties are severely degraded in a hydrogen ambient atmosphere. By controlling the polarity of the capacitors in a ferroelectric memory during the manufacturing process, the amount of degradation can be significantly reduced. After metalization of a ferroelectric memory wafer, all of the ferroelectric capacitors are poled in the same direction. The polarization vector is in a direction that helps to counteract hydrogen damage. A hydrogen gas anneal is subsequently performed to control underlying CMOS structures while maintaining ferroelectric electrical properties. The wafer is then passivated and tested.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: May 29, 2001
    Assignee: Ramtron International Corporation
    Inventors: Shan Sun, Steven D. Traynor
  • Patent number: 6232153
    Abstract: A plastic package assembly method suitable for ferroelectric-based integrated circuits includes a strict thermal budget that reduces the time at temperature for four key processing steps: die attach cures, die coat cures, molding cures, and marking cures. The plastic package assembly method uses low temperature mold and die coat materials, as well as low temperature curable inks or laser marking in order to minimize degradation of electrical performance, thus improving yields and reliability. The assembly method uses a snap cure die attach step, a die coat followed by a room temperature cure, and formation of the plastic package with room temperature curable molding compounds not requiring a post mold cure. Front and back marking of the plastic package is accomplished using either an infrared or ultraviolet curable ink followed by minimum cure time at elevated temperature, or by using laser marking.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: May 15, 2001
    Assignee: Ramtron International Corporation
    Inventors: Sanjay Mitra, Vic Lau
  • Patent number: 6226077
    Abstract: A highly precise range measurement instrument is made possible through the use of a novel and efficient precision timing circuit which makes use of the instrument's internal central processing unit crystal oscillator. A multi-point calibration function includes the determination of a “zero” value and a “cal” value through the addition of a known calibrated pulse width thereby providing the origin and scale for determining distance with the constant linear discharge of capacitor.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: May 1, 2001
    Assignee: Laser Technology, Inc.
    Inventor: Jeremy G. Dunne
  • Patent number: 6212480
    Abstract: An apparatus and method for measuring coefficients of retroreflectance of retroreflective surfaces such as road signs involves use of a modified light based range finder. The apparatus includes a power attenuation factor data base which relates pulse width of received pulses to power attenuation of the transmitted pulses. The range finder calculates target range based on time of flight of light pulses. The apparatus automatically calculates the absolute coefficient of retroreflectance for an unknown reflective surface being measured by comparison of the measurement to a reading with the same instrument of a known reflectance standard.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: April 3, 2001
    Assignee: Laser Technology, Inc.
    Inventor: Jeremy G. Dunne
  • Patent number: 6200170
    Abstract: Racks of modules especially useful for retaining disk drives, tape drives, controllers, computers and the like are fabricated via use of tower building blocks. Each block contains a latch arrangement for securing it to another block, a base unit or a cap unit with the latch effecting interlocking of the blocks so as to form a sturdy assembled structure. Power and/or electrical communication lines are provided in each block with power passing through one vertical array of blocks and electrical communications passing through the other so as to reduce the need for shielding one from the other. An arrangement of alignment pins and mating receptacle holes in conjunction with selected placement of sliding latch elements can facilitate proper coupling of blocks which have similar electrical path boards therein. Spring elements contained in the latch configuration can include biasing to overcome tolerance build-up and plastic creep from repeated and long term usage.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: March 13, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Mark Frederick Amberg, Allen Walter Clark, Benjamin Alma Young
  • Patent number: 6185123
    Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: February 6, 2001
    Assignee: Ramtron International Corporation
    Inventors: Judith E. Allen, William F. Kraus, Lark E. Lehman
  • Patent number: 6172927
    Abstract: An integrated circuit first-in, first-out (“FIFO”) memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory (“DRAM”) array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory (“SRAM”) row, or register, interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: January 9, 2001
    Assignee: Ramtron International Corporation
    Inventor: Craig Taylor