Abstract: Via holes in a thin planar layer of unfired ceramic which consists essentially of a mixture of an inorganic nonmetallic powder having a high melting temperature and a binder having a lower vaporizing temperature, are formed by the steps of: directing a laser beam, in a sequence, at certain locations on the layer where the via holes are to be formed; controlling the power density in the directed laser beam to a low level at which the binder vaporizes at each of the locations while the powder stays unsintered and unmelted; and removing from the directed laser beam during the above steps, both the vaporized binder and the unbound powder which remains where the binder vaporizes. Preferably, the vaporizing temperature of the binder and the melting temperature of the binder and the melting temperature of the powder are selected such that they differ by at least 200.degree. C.; the power density of the laser is controlled to be between 5 kW/cm.sup.2 and 75 kW/cm.sup.

Abstract: A tester for measuring the time with which a signal propagates through an electronic component is comprised of a ring oscillator in which pulses are periodically generated and propagated around a loop. Within this loop, a fixture is disposed for selectively holding either the electronic component that is to be tested, or a shorting plug, in a removable fashion. Pulses from the ring oscillator propagate through the fixture, and their period reflects whether the component/shorting plug is being held. Coupled to the loop is a timing circuit which generates a timing signal each time it receives a predetermined number of the pulses on the loop. Using this timing signal, the signal propagation delay through the electronic component is determined substantially more accurately than that which is attainable by measuring propagation delay through the component directly.

Abstract: An emulator is comprised of a host processor, an emulator, assist unit, and a memory which are closely coupled together over a co-processor bus. Stored in the memory is a user program which is a sequence of instructions from a user instruction set that is to be emulated, and a control program which is a mixture of host processor instructions and emulator assist unit instructions. In operation, the host processor reads and executes the hosts instructions, and it reads and passes the emulator assist unit instructions to the emulator assist unit for execution in that unit. By this means, the host processor and the emulator assist unit share the emulation tasks; and those tasks which are most difficult for the host are performed by the emulation assist unit.

Abstract: A multichip integrated circuit module includes a ceramic substrate, a plurality of integrated circuit chips mounted on the substrate, and a metal lid which covers the chips and rests on the substrate without attaching to it. Also, the module includes two thin cylindrical members. One cylindrical member surrounds the substrate and makes an airtight solder joint to the substrate's perimeter, while the other cylindrical member surrounds the lid and makes an airtight solder joint to the lid's perimeter. Both cylindrical members run parallel to each other and make an airtight welded joint with each other. When the lid and substrate thermally expand at unequal rates, one thin cylindrical member is deflected by the other member. When a defective chip is replaced, the joint between the two cylindrical members is ground away; and subsequently, the remaining parallel portions of the cylindrical members are rewelded together.

Abstract: A leak tolerant liquid cooling system for electrical components comprises a cooling circuit which contains a pump and conduits that circulate a liquid coolant past the electrical components and through the bottom chamber of a purge tank. This purge tank also has a top chamber which is connected to the bottom chamber through a passageway; and, the bottom chamber is sized such that the liquid coolant passes through it with a velocity which is low enough to let any air bubbles in the coolant rise and move by buoyancy through the passageway into the top chamber. Air is purged from the top chamber through a valved output port by forcing liquid coolant into the top chamber through a valved input port. To complete this purge quickly, the passageway between the purge tank chambers is configured in a way which hinders the flow of coolant from the top chamber to the bottom chamber while the coolant is being forced into the top chamber.

Abstract: A digital BiCMOS memory chip includes a row of memory cells, and an addressing circuit for the row of cells. Each of the memory cells is constructed of field-effect transistors which operate at CMOS voltage levels, whereas the address decorder is constructed of bipolar transistors which operate at ECL voltage levels. A direct connection is made via a row line from the address decoder to the row of memory cells with no ECL-to-CMOS voltage level converter lying there between. This direct connection is made operable by properly selecting all voltages that occur on certain nodes in the address decoder and the memory cell. And, it enables the memory to be read faster plus occupy less chip space and dissipate less power than the prior art.

Abstract: A composite signal is formed by simultaneously transmitting multiple asynchronous data bit sequences, that are coded with respective spreading codes, in a single channel; and a circuit is provided which decodes any bit b(x) in that composite signal. This circuit includes a set of filters which are matched to all of the spreading codes and which obtain (a) a matched filter output signal y(x) for the x-th data bit b(x) and (b) matched filter output signals y(x+1) thru y(x+k-1) for the k-1 data bits that immediately follow data bit b(x); K is the number of bit sequences in the composite signal. An arithmetic unit combines the matched filter output signals via the expression: ##EQU1## where H(x,x.+-.i) is the cross correlation of the spreading codes for data bits b(x) and b(x.+-.i) over the time period that those data bits overlap (and thus add) in the composite signal, and ESTb(x-i) is an estimate of data bit b(x-i) which precedes bit b(x).

Abstract: A high density integrated circuit module is comprised of a plurality of integrated circuit chips; each of the chips has top and bottom surfaces and thin sides; and all of the chips are arranged in a stack in which the sides of the chips form multiple faces of the stack. Also, in accordance with the invention, a selected face of the stack has a zigzag shape which exposes a portion of the top surface of each chip on that face; and, bonding pads for carrying input/output signals to/from the chips are located on the exposed top surface portion of the chips. This zigzag shape is produced by (a) providing an indentation in the side of each of the chips which lie along the selected stack face; or (b) by offsetting the sides of the chps from each other as they lie along the selected stack face; or (c) by providing respective spacers between the chips and indenting them from the chips along the selected stack face.

Abstract: A module for preventing instability in systems which test integrated circuit chips resides between the tester unit and the chip that is being tested. This module is characterized as including a plurality of phase-shifting circuits which couple respective output signals from output transistors on the chip onto signal lines to the tester unit. Each phase-shifting circuit includes an inductor which counteracts and cancels any capacitive phase shift that is produced by the input impedance of the corresponding signal line to the tester unit.

Abstract: A socket for an electronic component is comprised of an electrically insulative base having patterned electrical conductors integrated therein; a plurality of electrically conductive springs are held by the base; the springs are arranged in a pattern such that they can be compressed perpendicular to a plane by respective input/output terminals on the component; and, each spring is a sponge-like mass which is forced against a respective one of the conductors in a direction parallel to the plane in response to being compressed perpendicular to the plane by the component's terminals.

Abstract: Interconnect circuitry is formed on a selected face of several separate layered electronic assemblies simultaneously. This circuitry interconnects the I/O leads on each assembly, and it is formed by the steps of: (a) placing a plurality of the assemblies in a fixture with spacers between each assembly; (b) aligning to a single plane, one face of each assembly in the fixture on which the circuitry is to be formed; (c) mechanically squeezing the assemblies and spacers together with the fixture such that the aligned faces are held in the single plane and are exposed; (d) depositing and patterning layers of insulative and conductive materials on all of the exposed faces in the fixture; and (e) severing the layers between the faces in the space provided by the spacers. With this process, beading effects in materials that are spun onto the assemblies are eliminated; handling damage to the assemblies is eliminated; and the time and expense of processing one assembly separately is cut by several hundred percent.

Abstract: A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set a reset nodes. Also in each cell, a first P-channel transistor couples a first select line to the set node; a first bipolar transistor couples the set node to a first bit line; a second P-channel trnasistor couples a second select line to the reset node; and a second bipolar transistor couples the reset node to a second bit line. Data is read from one port of the cell by pulling up just the set node via the first selected line and first P-channel transistor; and data is read from another port of the cell by pulling up just the reset node via the second select line and second P-channel transistor. Both such reads are fast since the parasitic capacitance of each select line is dependent on just a single pull-up transistor per cell. Also the cell is small in size since it is made with two less transistors than a conventional cell.

Abstract: A given target temperature profile T is produced in a workpiece as it passes through an elongated passageway of a belt furance by the steps of: (1) determining a set of temperature setting TS.sub.X for the belt furnace thermostats which satisfy an equation f(.alpha.,TS.sub.X,CF.sub.Y).apprxeq.T where .alpha. is a set of thermal parameters for the workpiece, CF.sub.Y is a set of correction factors, and f( ) is a function which approximates the temperature of said workpiece based on TS.sub.X,.alpha., and CF.sub.Y ; (2) measuring an actual temperature profile A(TS.sub.X) of the workpiece in the furnace with the heater thermostats at the settings TS.sub.x ; (3) terminating if the measured actual temperature profile A(TS.sub.X) matches the target temperature profile T within a predetermined tolerance; otherwise, (4) determining a new set of correction factors which satisfies an equation f(.alpha.,TS.sub.X,CF.sub.Y)=A(TS.sub.X); and thereafter repeating the above steps.

Abstract: Layered electronic assemblies are fabricated from a plurality of integrated circuit chips that have respective thicknesses which vary from chip to chip, and have I/O leads which are offset from one edge of the chip on which they lie by respective distancess which vary from chip to chip.

Abstract: An electronic system for processing sampled data input signals includes an electronic memory which stores a set of preprocessed vectors V.sub.1 f(m, . . . ) thru V.sub.N *f(m, . . . ) where f(m, . . . ) is a sampled data function, having any number of dimensions m, . . . . * is a convolution operator, and V.sub.1 thru V.sub.N are a finite set of N unprocessed vectors each of which represents an anticipated group of input signal samples.

Abstract: A layered electronic assembly contains a plurality of integrated circuit chips that are arranged in a stack; respective adhesive layers interleave the chips and hold them together; and I/O leads on the chips extend to one face of the stack. Also, the chips in the stack have respective thicknesses which vary from chip to chip; the I/O leads are offset from one edge of the chip on which they lie by respective distances which vary from chip to chip; the adhesive layers in the stack have respective thicknesses which compensate for the thickness variations in the chips such that the I/O leads on adjacent chips are spaced by predetermined distances along the stack face; and the chips are shifted relative to one another such that their one edge is misaligned while their I/O leads are aligned on the stack face. This layered electronic assembly uses 100% of the electrically functional chips which are cut from a semiconductor wafer without sacrificing any accuracy with which the I/O leads are aligned on the stack face.

Abstract: A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.

Abstract: A digital translator, on a semiconductor chip that contains N-channel transistors and P-channel transistors which have threshold voltages that vary about respective nominal values, includes an input/output module which is made of the transistors and which receives a digital input signal at two voltage levels and in response generates a digital output signal at two different voltage levels. To compensate for the threshold variations and thereby stabilize the voltage levels of the output signal, the translator also includes a voltage generator which produces a reference voltage for the input/output module.

Abstract: Disclosed is a digital computer having memory means stacked on an insulating layer over a semiconductor substrate. In one embodiment, the memory means includes an array of diodes which overflies the substrate and generates control signals for an arithmetic section that lies in the substrate; and in another embodiment, the memory means includes N arrays of diodes which overlie the substrate and operate in parallel to generate signals representing arithmetic transformation of a portion of their address inputs.

Abstract: An electro-mechanical probe is comprised of a thin flat ring-shaped frame, and an elastic transparent membrane which is attached to a downward-facing surface of the ring-shaped frame and which traverses the aperture of the ring. On this membrane are a plurality of microscopic conductive bumps which are aligned with and which are outside of the aperture of the ring. Also integrated into the membrane are a plurality of microscopic conductors, and they serve as a means for sending electrical signals to and receiving electrical signals from the bumps. In operation, the probe frame is fitted with a cover which overlies the elastic membrane to thereby form an enclosed chamber. Both the cover and the elastic membrane are transparent so that the bumps on the membrane can be aligned with corresponding contacts on a semiconductor chip or interconnect module which is to be tested.