Abstract: A CMOS voltage controlled current source is described for furnishing current to a load in a charging mode and to receive current from a load in a discharging mode of operation. This bi-lateral current source is voltage controlled and provides a current which is proportional to the applied voltage. The current flow into, and out of the current source changes in a linear fashion and varies proportional to the input control voltage. This bi-lateral current source is made from all CMOS devices.
Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to a control register, the data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers.
October 30, 1974
Date of Patent:
September 7, 1976
Thomas H. Bennett, Earl F. Carlow, Michael F. Wiles
Abstract: An asynchronous interlock circuit for an interface adaptor circuit in a digital system includes a D-type latch, a D-type flip-flop, and an RS-type flip-flop interconnected to accept a peripheral status input from a peripheral equipment unit, a read status input and a read data input derived from control and selection inputs to the interface adaptor from a microprocessor unit of the digital system. The asynchronous interlock circuit stores information corresponding to a logical "1" on the peripheral status interrupt input in the D-type flip-flop, even if the latter signal disappears prior to acknowledgment by the microprocessor of a corresponding interrupt signal generated by the interface adaptor circuit. The D-type flip-flop is reset by a sequence of a read status signal and a read data signal, thereby avoiding problems which could arise if the peripheral status input remains at a logical "1" even after acknowledgment by the microprocessor unit of an interrupt signal generated by the interface adaptor.
Abstract: An oscillator is provided the frequency of operation of which is controlled by an RC circuit the resistive element of which is an MOS load device and the capacitive element of which is an MOS enhanced capacitor. An important characteristic of this ring oscillator is that its time constant determining elements mutually compensate one another for changes in temperature. A digital enhanced capacitor can be used in this temperature compensated ring oscillator to provide greater flexibility in controlling both the frequency of operation of the oscillator and the wave shape of the output signal.
Abstract: An integrated circuit includes circuitry thereon which includes a sensor circuit which detects a change in one of the plurality of inputs to the integrated circuit and generates one or more pre-conditioning signals which control circuitry to set up voltage at various nodes in the integrated circuit to facilitate fast processing of data signals from inputs of the integrated circuit to outputs thereof. Embodiments of the sensor circuit include integrated memory circuits and integrated micro-processor circuits.
Abstract: An integrated circuit asynchronous communications interface adapter (ACIA) includes circuitry on a semiconductor chip for interfacing with a bidirectional data bus of a microcomputer. Bus interface circuitry on the ACIA chip controls data transfer between the microcomputer data bus and a transmit data register and a read data register on the ACIA chip. Transmitting circuitry on the ACIA chip converts data from a parallel format to a serial format. Receiving circuitry on the ACIA chip accepts data in a serial format and converts it to a parallel format prior to transferring it to a receive data register. A control register controls data transfer throughout the ACIA chip. A status register on the ACIA chip may be interrogated under program control to determine the status of registers and/or correctness of data format, status of interrupt logic or modem control lines.
February 18, 1975
Date of Patent:
August 17, 1976
Edward C. Hepworth, Rodney J. Means, Charles I. Peddle
Abstract: An interface circuit for integrated circuit devices which prevents deleterious injection of minority carriers into the substrate during overvoltages applied to a terminal of the integrated circuit. A lateral PNP transistor formed in an N-type region has its base connected to a bias circuit and its collector connected to a load circuit and its emitter connected to a current source having a P-type electrode. The emitter is also connected to a first terminal of the integrated circuit. If the first terminal is connected to a signal wire having large negative noise pulses thereon, the emitter-base junction of the lateral PNP transistor will become reverse biased during the negative pulses, thereby preventing the injection of minority carriers into the P-type substrate in which the integrated circuit is fabricated.
Abstract: A bipolar sense-write circuit is provided for sensing voltage levels representative of a logical "1" or "0" stored in a flip-flop storage cell and for writing voltage levels into the flip-flop storage cell. The sense-write circuit includes first and second amplifier stages which, when coupled to a selected flip-flop storage cell produce a voltage in the amplifier section approximately equal to the voltage on a collector node in the flip-flop storage cell. Each amplifier stage of the sense-write circuit utilizes a side of the selected flip-flop storage cell as a part of that amplifier stage, if the corresponding side of the flip-flop storage cell is "on". The amplifier stage connected to the "on" side of the selected flip-flop storage cell acts as a unity gain amplifier, such that the row selection voltage appears at the output of that amplifier stage.
July 11, 1975
Date of Patent:
August 3, 1976
Michael S. Millhollan, Ronald L. Treadway
Abstract: The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers arranged along an opposite edge of the chip and a register section centrally located on the chip. Separate power supply buses are used to supply a ground voltage to the buffer and register sections. Data bus buffers are arranged to allow the pins of the enclosing semiconductor package to correspond to data bus pins of a separate microprocessor chip. Register sections are offset on the surface of the peripheral interface adaptor chip in such a way as to facilitate nesting of the conductors coupled to the buffer circuit section. Identical buffer cells and custom drawn cells are both utilized so as to optimize use of semiconductor chip area.
Abstract: A speed-up circuit, which may be used to speed up the sensing of a bit-sense line of an MOS RAM, includes a crosscoupled latch circuit having an output suitable for coupling to an output circuit for the RAM. A plurality of bit-sense lines of the RAM storage array are coupled to load circuitry for one side of the latch circuit. When partial discharging of a bit-sense line by a selected memory cell occurs, the latch circuit switches state and provides feedback internal to the latch circuit and other feedback external to the latch circuit to aid the selected memory storage cell in discharging a bit-sense line much more rapidly than could have been achieved by the action of the selected storage cell alone, and also assures complete discharging of the bit-sense line, which avoids destroying stored data in the selected memory cell during a refresh cycle. The external feedback is coupled to discharge devices connected to the various bit-sense lines serving various sections of the memory array.
Abstract: A program register is coupled between a data bus N bits wide and an address but N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. for certain instructions, the address bus is be utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter depending on the type of instruction being executed.
Abstract: A family of comparators are described which utilize only MOSFET transistors as the active devices. These comparators exhibit an infinite input impedance and zero input offset and bias currents. The circuits are capable of operating over a wide range of DC supply voltages at extremely low DC current drain. A comparator is shown which operates from a single positive DC supply voltage and which handles a wide range of input common mode (reference) voltages including some negative common mode voltages. Another comparator is shown which operates from a combination of a single positive and a single negative supply voltage and which handles a wide range of positive and negative input common mode voltage swings (references).
Abstract: A family of differential amplifiers are described which utilize only MOSFET transistors as the active devices. These amplifiers exhibit an infinite input impedance and zero input offset and bias currents. The circuits are capable of operating over a wide range of DC supply voltages at extremely low DC current drain. A differential amplifier is shown which operates from a single positive DC supply voltage and which handles a wide range of input common mode voltage swings including some negative common mode voltages. Another amplifier is shown which operates from a combination of a single positive and a single negative supply voltage and which handles a wide range of positive and negative input common mode voltage swings.
Abstract: A method for manufacturing a low cost high frequency transistor package including a metal header, a metallized apertured ceramic insulator affixed to the header, a metallized beryllia insulator, and two cylindrical bonding rails within the aperture of the ceramic insulator attached to the header. The two bonding rails may be segments of wire. Metal leads are attached to the ceramic insulator. A very low inductance path through the bonding rails to the header results.
Abstract: A multi-state CMOS synchronous binary counter is implemented utilizing a CMOS transmission gate look-ahead carry circuit requiring only a fraction of the area required for AND or NAND gate carry structures.
Abstract: A MOSFET voltage booster circuit generates a stepped up DC voltage from a lower magnitude supply voltage and a periodic input signal. A plurality of such MOSFET voltage booster circuits, which are formed only from components integrated in the MOSFET integrated circuit chip, may be formed on the chip near corresponding sections of circuitry requiring a high DC bias signal. A free-running oscillator circuit may provide the required periodic input signal.
Abstract: An edge sensing circuit is implemented using MOS logic gates. The edge sense circuit detects either a positive transition or a negative transition of a first input signal, depending on the logic level of a second input signal, if an enable signal logical "1" is applied to the edge sense circuit. If the enable signal is at a logical "0," however, a level, rather than a transition, of the input signal is detected.
Abstract: An integrated circuit includes circuitry thereon which includes a sensor circuit which detects a change in one of the plurality of inputs to the integrated circuit and generates one or more pre-conditioning signals which control circuitry to set up voltages at various nodes in the integrated circuit to facilitate fast processing of data signals from inputs of the integrated circuit to outputs thereof. Embodiments of the sensor circuit include integrated memory circuits and integrated micro-processor circuits.
Abstract: A two of eight tone encoder utilizing digital techniques to synthesize the dual tones of a Touch Tone telephone operator system is provided. One of sixteen switches from the telephone keyboard selects one of four desired row tones and one of four desired column tones. The two of eight encoder circuit includes, for the row encoding section, a counter which is programmable by the row input signals. The counter output drives a plurality of exclusive OR gates and a one of eight decoder which switches one of eight resistors into a resistive divider network. The exclusive OR gates and the one of eight decoder cooperate to perform an up-down counting function. The eight resistors are chosen in value so that a synthesized stepped sine wave is generated at the output of the resistive divider network, the synthesized stepped sine wave corresponding to the desired selected row frequency. Similar circuitry generates a stepped sine wave corresponding to the desired selected column frequency.
Abstract: A speed-up circuit for a bit sense line of an MOS RAM includes a cross-coupled latch circuit having an output coupled to the bit sense line. When partial discharging of the bit sense line is accomplished through the selected storage cell, the latch circuit switches states and completes discharge of the bit sense line much more rapidly than could have been achieved by the action of the selected storage cell alone. A disabling circuit is connected to the gate of a pull-down MOSFET of the latch circuit connected to the output thereof to turn off the pull-down MOSFET during a write cycle or during the write portion of a read-modify-write cycle. The output of the disabling, or turn-off, circuit operates in response to a signal derived from a clock signal and a chip enable signal applied to the MOS RAM. A bootstrap circuit is provided including a bootstrap charging MOSFET having its gate coupled to V.sub.