Patents Represented by Attorney Christopher L. Maginniss
  • Patent number: 5767526
    Abstract: A solid-state frequency multiplier circuit (10) is provided which includes a bipolar quantum-well resonant tunneling transistor (12), a resistive load (14), and an A.C. output coupling capacitor (16), all which may be formed in a single integrated circuit or as discrete components. The value of the resistive load (14) determines the frequency multiplication factor of the circuit (10), and can produce frequencies in a range from about 2 GHz to over 20 GHz. A different embodiment of the present invention provides a frequency multiplication circuit (20) which generates a sinusoidal output waveform, without using an output A.C. coupling capacitor.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: June 16, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Alan C. Seabaugh
  • Patent number: 5760643
    Abstract: An integrated circuit die includes structure (73, 75, 77, 79) for permitting selective pad-to-pad bypass of its internal circuitry.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: June 2, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 5757000
    Abstract: A focal plane array (30) for a thermal imaging system (20). The focal plane array (30) may include a number of thermal sensitive elements (42) formed by a first series of slots (78) and a second series of slots (80). The thermal sensors (40) may be bounded by a border (41). The thermal sensors (40) may provide a sensor signal output representative of thermal radiation incident to the focal plane array (30). The first series of slots (78) may include a leading first slot (82) and a trailing first slot (84). Additionally, the first series of slots (78) may include a number of substantially parallel first slots therebetween. The second series of slots (80) may include a leading second slot (86) in a trailing second slot (88). The second series of slots (80) may also include a number of substantially parallel second slots therebetween. One of the first slots may extend beyond the leading second slot (86). Additionally, one of the first slots may extend beyond the trailing second slot (88).
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: May 26, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Donald A. Rogowski, John P. Long
  • Patent number: 5751049
    Abstract: A two-color infrared detector (50) is provided comprising elements (10, 110, or 210) having one or more diodes (58, 158 and 168) and a metal insulator semiconductor ("MIS") device (56 and 156). The infrared detector (50) may be referred to as a vertically integrated capacitor diode. The diodes comprise regions (12, 14, 16, 112, 114, and 116) of semiconductor materials which are operable to generate electron-hole pairs when struck by infrared radiation (40) having first and second wavelengths. The capacitor (156) includes a gate (24) provided by the MIS device which is operable to generate a potential well in the first semiconductor region (12 and 112) in conjunction with an insulator layer (22) and collect charges generated by the first wavelength of infrared radiation (40). The layers of semiconductor material may be varied to enhance the performance of the resulting infrared detector.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: May 12, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Michael W. Goodwin
  • Patent number: 5744949
    Abstract: An electrical circuit with test capability includes an analog signal path for carrying an analog signal, first and second nodes for use in testing the analog signal path, a first switching element connected to the first node, a second switching element connected to the second node, and a third switching element connected between the analog signal path and the first and second switching elements, whereby first and second test signal paths are respectively provided between the analog signal path and the first and second nodes.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: April 28, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 5744375
    Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.z Ga.sub.1-z,As (106), next annealing out defects with the Al.sub.z Ga.sub.1-z As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: April 28, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Yung-Chung Kao, Donald L. Plumton
  • Patent number: 5736425
    Abstract: This invention has enabled a new, simple nanoporous dielectric fabrication method. In general, this invention uses a glycol, such as ethylene glycol, as a solvent. This new method allows both bulk and thin film aerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Prior art aerogels have required at least one of these steps to prevent substantial pore collapse during drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although not required to prevent substantial densification, this new method does not exclude the use of supercritical drying or surface modification steps prior to drying. In general, this new method is compatible with most prior art aerogel techniques. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: April 7, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas M. Smith, William C. Ackerman
  • Patent number: 5733160
    Abstract: A method disclosed herein for making a spacer 30 useful for maintaining a fixed spacing between the cathode 12 and anode 10 structures of a flat display. The method includes the steps of melting an end of a glass filament 40 held in the bore of a capillary 42, urging the melted end 46 against the surface 23 of the cathode structure 12 to form a bond thereon, and severing the filament 40 at a fixed distance h from the surface 23 to thereby form an upright spacer 30. The severing step may be accomplished by tilting or twisting the capillary 42 until the filament 40 is severed, or by cutting the filament 40 with a torch flame 54. The bonding process may be enhanced by preheating the cathode structure 12 and/or by subjecting the cathode structure 12 to ultrasonic vibration during bonding.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: March 31, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Shin-Puu Jeng, Johnson J. Lin, Bruce E. Gnade, Dennis I. Robbins
  • Patent number: 5717231
    Abstract: A flip-chip integrated circuit having passive 302, 304, 306 as well as active 308, 310 components on a frontside surface of a substrate. The active device have airbridges which contact a heatsink to provide heat dissipation from the junctions of the devices.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: February 10, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Hua Quen Tserng, Paul Saunier, Shashikant M. Sanzgiri
  • Patent number: 5710068
    Abstract: A frontside ground plane (306) integrated circuit with backside contacts (312) plus optional passive components such as microstrip (308) and capacitors. The frontside ground plane provides direct heat dissipation from active junctions such as heterojunction and field effect transistors.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 20, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Darrell G. Hill
  • Patent number: 5710604
    Abstract: A field emission device (10) includes a video memory device (12) that receives video data in parallel for each of three colors red, green, and blue. The video memory device (12) provides the video data in color sequential manner to a controller (14). The controller (14) provides appropriate control and data signals in response to the video data to drive a field emission device display (22). The video memory device has a first storage area (30) for a first color (red), a second storage area (32) for a second color (green), and a third storage area for a third color (blue). The second storage area (32) has capacity to store all of the second color of a frame, the first storage area (30) is two-thirds the size of the second storage area (32), and the third storage area (34) is one-third larger than the second storage area (32). The different sizes of the respective storage areas allows for 100% use of memory space without waste.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: January 20, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Lester L. Hodson, Ulrich Skowronek, Charles E. Primm
  • Patent number: 5702958
    Abstract: The invention described herein includes, in one of its forms, a method for fabricating a semiconductor device having ledge material (148, 150, 152, 162) extending over an undercut region. The method comprises the step of forming a layer of material 164 in tensile stress over the undercut region, or region to be undercut. The layer of material in tensile stress can be a dielectric, such as silicon nitride, and provides support for the ledge material in subsequent processing steps.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: December 30, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: William U. Liu, Darrell G. Hill
  • Patent number: 5700701
    Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 23, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Darrell Hill, Shou-Kong Fan, Ali Khatibzadeh
  • Patent number: 5698460
    Abstract: A self-aligned planar heterojunction bipolar transistor (10) is fabricated by forming a base layer (18) and forming an emitter layer (20) on the base layer (18). An emitter cap layer (22) is formed on the emitter layer (20) and an interface layer (24) is formed on the emitter cap layer (22). A first implantation layer (26) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18). A second implantation layer (30) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18) and overlaps the first implantation layer (26). A portion of the interface layer (24), the emitter cap layer (22), and the implantation layers (26, 30) are removed and replaced by an insulating region (33). An emitter contact (38) is formed on the remaining emitter cap layer (22) and is isolated from the implantation layers (26, 30) by the insulating region (33).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 16, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jau-Yuann Yang, Donald L. Plumton, Francis J. Morris
  • Patent number: 5689151
    Abstract: An anode plate (10) for use in a field emission flat panel display device (8) comprises a transparent substrate (26) having a plurality of spaced-apart, electrically conductive regions (28) which form the anode electrode of the display device (8). The conductive regions (28) are covered by a luminescent material (24). A getter material (29) is deposited on the substrate (26) and between the conductive regions (28) of the anode plate (10). The getter material (29) is preferably an electrically nonconductive, high porosity, and low density material, such as an aerogel or xerogel. Methods of fabricating the getter material (29) on the anode plate (10) are disclosed.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: November 18, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, John M. Anthony, Bruce E. Gnade, Chih-Chen Cho
  • Patent number: 5684356
    Abstract: An emitter structure 12 for use in a field emission display device comprises a ballast layer 17 overlying ah electrically conductive coating 16 (cathode electrode), which is itself formed on an electrically insulating substrate 18. A gate electrode comprises a coating of an electrically conductive material 22 which is deposited on an insulating layer 20. Cone-shaped microtips 14 formed within apertures 34 through conductive layer 22 and insulating layer 20. In the present invention, insulating layer 20 comprises a dielectric material capable of desorbing at least ten atomic percent hydrogen, which may illustratively comprise hydrogen silsesquioxane (HSQ). HSQ is an abundant source of hydrogen which keeps deleterious oxides from forming on microtip emitters 14. HSQ also reduces the capacitance formed by cathode electrode 16 and gate electrode 22, since its relative dielectric constant is less than 3.5.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: November 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Shin-Puu Jeng, Bruce E. Gnade
  • Patent number: 5684310
    Abstract: Generally, and in one form of the invention, a multiple layer wide bandgap collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.
    Type: Grant
    Filed: August 10, 1993
    Date of Patent: November 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: William Uei-Chunt Liu
  • Patent number: 5683919
    Abstract: A flip-chip integrated circuit having a transistor 300 with terminals 314, 312, 320 contacted from opposite sufaces of a semiconductor substrate 302. The terminals contacted from opposite surfaces of the substrate may be vertically aligned. The active devices may also be etched or implanted to reduce parasitic capacitances and therefore improve transistor performance.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Hua Quen Tserng
  • Patent number: 5680280
    Abstract: A magnetic sensor using heterojunction transistors for detecting magnetically recorded data. The sensor has a pair of heterojunction transistors T1, T2 connected in a differential circuit disposed on a substrate 18. The substrate 18 is carded on the free end of a suspension arm 12 at a distance D from the surface of a disk 14 having magnetically recorded data thereon. The transistors are disposed a distance S apart which is selected with D so that the magnetic field direction at one transistor is generally perpendicular to the disk 14 and the magnetic field direction at the other transistor is generally parallel to the disk 14 when a magnetic transition occurs immediately adjacent the magnetic sensor.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: October 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Carter Seabaugh, Gary A. Frazier
  • Patent number: 5673478
    Abstract: A method and an apparatus for I/O reroute include the use of reroute traces (16) and overhangs (20). The reroute traces (16) and overhangs (20) are formed using thick film deposition on dies that have been cut from a wafer.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Beene, Robert E. Terrill