Patents Represented by Attorney, Agent or Law Firm Columbia IP Law Group, PC
  • Patent number: 6512515
    Abstract: A computing-device implemented method for compressing a data model, where such devices include a computer, personal digital assistant (PDA), home appliance, and the like. The data includes bandwidth intensive information such as that used in video conferencing, MPEG and equivalent types of digital video encoding, multi-media data transfers, and interactive gaming. In one implementation, a 3D model has objects defined therein. Each object is defined by plural data points that are transferred from a data provider to a recipient. Typically the provider and recipient are in communication over a network. For a first and a second data point defined in the model, first offsets are determined from the first data point for the second data point. The second data point can then be re-coded in terms of the determined first offsets. The first offsets are coded to require less data storage than required for the first data point, thus allowing them to be transferred more quickly.
    Type: Grant
    Filed: September 18, 1999
    Date of Patent: January 28, 2003
    Assignee: WildTangent
    Inventors: Peter D. Smith, Jeremy A. Kenyon
  • Patent number: 6480816
    Abstract: An EDA tool is provided with a circuit simulator that simulates circuit operation using dynamic partitioning and on-demand evaluation. The circuit simulator includes a static partitioner, a dynamic partitioner and an evaluation scheduler. The static partitioner pre-forms a number of static partitions for the circuit. During simulation, the dynamic partitioner forms and re-forms a number of dynamic partitions referencing the static partitions. At each simulation time step, the evaluation scheduler determines which, if any, of the dynamic partitions have to be evaluated, and evaluating on-demand only those where evaluations are necessary. In one embodiment, when evaluations are performed, they are performed through matrix solution when accuracy is needed.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: November 12, 2002
    Inventor: Sanjay Dhar
  • Patent number: 6466133
    Abstract: A novel basic allergen data collection device and a novel multi-function personal asthma management device are disclosed. Both devices include sensor sub-assembly detecting and reporting on allergen data (preferably, for allergen with sizes smaller than 5 micron) for an indoor location (where the asthma patient is situated). Both devices are communication enabled to allow the allergen data to be provided to an air/asthma advice server, to generate air/asthma advice for an asthma patient, taking into consideration the allergen data as well as air quality data for a surrounding outdoor area of the indoor location. In one embodiment of the basic device, the communication interface is tailored for “harsh environment” local area networking. When combined with its streamlined functionality, the device is particularly suitable (especially in terms of economics) for multiple deployment (along with a “base station”), such as in the case of an home application.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: October 15, 2002
    Assignee: AirAdvice, Inc.
    Inventor: John N. Skardon
  • Patent number: 6466953
    Abstract: The invention includes computer instructions that receive an indication of a manipulation of one or more graphical icons by a user, where the graphical icons are interrelated to one another representing a hierarchical relationship among multiple objects of one or more sheets, and the sheets are included within a drawing by a computer aided design (CAD) application program. The computer instructions operate to automatically modify at least sheet order information included within the objects of the one or more sheets reflecting the hierarchical relationship among the multiple objects of one or more sheets based, at least in part, upon the received indication.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: October 15, 2002
    Assignee: Autodesk, Inc.
    Inventors: Christine M. Bonney, William E. Bogan
  • Patent number: 6467076
    Abstract: The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag identifier defines a set of properties for edge fragments. Edge fragments are tagged if they have the set of properties defined by the tag identifier. For instance, tag identifiers may define edge fragments that make up line ends or comers, or tag identifiers may define edge fragments that have predetermined edge placement errors. In various embodiments, functions can be performed on the tagged edge fragments. For instance, rule-based optical proximity correction (OPC) or model-based OPC can be performed on the tagged edge fragments. Other functions may mark tagged edge fragments in a visual display of the IC design, display the number of edge fragments having particular tags in a histogram, or identify particularly complex and error prone regions in the IC design.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: October 15, 2002
    Inventor: Nicolas Bailey Cobb
  • Patent number: 6448483
    Abstract: An apparatus is equipped to provide dance visualization of a stream of music. The apparatus is equipped with a sampler to generate characteristic data for a plurality of samples of a received stream of music, and an analyzer to determine a music type for the stream of music using the generated characteristic data. The apparatus is further provided with a player to manifest a plurality of dance movements for the stream of music in accordance with the determined music type of the stream of music.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 10, 2002
    Assignee: WildTangent, Inc.
    Inventors: Siang L. Loo, Jeremy A. Kenyon
  • Patent number: 6441837
    Abstract: Computer instructions for a Computer Aide Design (CAD) system that operate to automatically facilitate a user in manipulating geometric constraints associated with a first piece of geometry of a mechanical design, when executed, are disclosed. The computer instructions operate to facilitate the manipulation responsive to a location of a cursor, when the location is within a predetermined proximity of the first piece of geometry. In one embodiment, the computer instructions are part of a mechanical design software application.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: August 27, 2002
    Assignee: Autodesk, Inc.
    Inventors: Muri Lee Harding, Kevin M. Linscott
  • Patent number: 6434599
    Abstract: Visitation by a first on-line user to an information page of an information site is facilitated. Dynamic formation of a chat session for the first on-line user and a second on-liner user to chat with each other is also facilitated. The chat session, through which the first and second on-line users chat with each other, is then facilitated. In one embodiment, the chat session including its dynamic formation are facilitated by the information site. In another embodiment, the chat session including its dynamic formation are facilitated by a third party chat server. In one embodiment, the second on-line user is also visiting the same information page. In another embodiment, the second on-line user is merely visiting the same information site. In yet another embodiment, the second on-line user is visiting another information site. In one embodiment, visit by the first on-line user to a new information page of another information site, during the chat session, is also facilitated.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: August 13, 2002
    Assignee: Xoucin, Inc.
    Inventor: Swain W. Porter
  • Patent number: 6418323
    Abstract: A wireless mobile phone, is provided with a couple of buttons and complementary logic to facilitate entry and transmission of Morse code representations of alphanumeric data. As a result, a user may use the provided facilities to engage in non-verbal communication for sensitive subject matters in the middle of a call. In one embodiment, the complementary logic further facilitates echoing on a display, alphanumeric data corresponding to any entered Morse code representations. Additionally, each of the Morse code entry buttons includes one or more light emitting diodes (LEDs), and the LEDs are lit to visually echo the Morse code representations of any alphanumeric data entered through a standard input keypad.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: July 9, 2002
    Assignee: Wildseed, Ltd.
    Inventors: Walter G. Bright, Eric Engstrom
  • Patent number: 6400383
    Abstract: An element selection is made in reference to a first graphical display showing a first subset of elements of a design having a number of elements coupled to one another. The selection is learned. In response, a second graphical display is provided. The second graphical display shows a second subset of the elements of the design, including at least a number of elements that are not part of the first subset but having an informational nexus to the selected element. As a result, a designer may selectively explore a complex design at the designer's direction.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: June 4, 2002
    Inventors: Stephen J. Geisler, Geetha Pannala
  • Patent number: 6396343
    Abstract: The instrumentation amplifier circuit of the present invention is particularly suited for amplifying ECG signals, rejecting common mode signals and removing a DC offset. The preferred embodiment of the present invention basically comprises a front-stage differential amplifier, and a common-mode rejection circuit. By employing a twin-T network, the front stage differential amplifier is able to simultaneously remove the DC offset and achieve high gain using standard off-the-shelf components. The common mode differential gain, however, is zero, which is the desired result. The common-mode rejection circuit removes the common-mode signal to yield only the amplified ECG signal. The present amplifier circuit has a much greater DC offset tolerance than the prior art amplifier while the Common Mode Rejection Ratio (CMRR), residual noise at the output, and the input dynamic range is comparable to that of the prior art amplifier. Moreover, it requires fewer operational amplifiers.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: May 28, 2002
    Assignee: Ngee Ann Polytechnic
    Inventor: Johnny Chee
  • Patent number: 6397172
    Abstract: An IC design computer simulation tool is provided with a design reader equipped to assign device characterizations to electronic devices of an IC design, and model evaluators equipped to adaptively perform model evaluations in accordance with the electronic devices' assigned device characterizations. In one embodiment, the electronic devices include transistors, and the adaptive model evaluations provide evaluated model quantities to support solution of the circuit node voltages using fully coupled (implicit) or partially decoupled (explicit) solution techniques. In particular, the transistor capacitive coupling currents are expressed according to the assigned device characterizations.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: May 28, 2002
    Inventor: David J. Gurney
  • Patent number: 6397372
    Abstract: An EDA tool is provided with the ability to determine a cell based parallel verification order for a plurality of hierarchically organized design cells of an integrated circuit design, and the ability to verify the design cells in accordance with the cell based parallel verification order, with at least some of the design cells being verified in parallel. In one embodiment, the EDA tool is also provided with the ability to re-express a design cell of the IC design in terms of a number of newly formed intervening constituent design cells, with the new intervening constituent design cells being formed in accordance with a number of metrics profiling placements of original constituent design cells of the design cell.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: May 28, 2002
    Inventors: Zeki Bozkus, Laurence W. Grodd
  • Patent number: 6388465
    Abstract: A number of enhanced logic elements (LEs) are provided to form a [FPGA] reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved [FPGA] IC may further comprise[s] a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: May 14, 2002
    Inventors: Jean Barbier, Olivier LePape, Frederic Reblewski
  • Patent number: 6389130
    Abstract: The distributed architecture switch of the invention provides a scalable, flexible switching device to route telephone calls and other data (e.g., frame relay, ISDN) over an asynchronous transfer mode (ATM) network. The switch includes multiple service modules that can be geographically disparate and function as a single switching device. The multiple service modules are coupled to a system controller that controls the service modules and passes messages between the service modules.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: May 14, 2002
    Assignee: Oresis Communications
    Inventors: George Shenoda, Andrew P. Alleman
  • Patent number: 6381731
    Abstract: An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a number of hierarchically organized placements of design cells. The new intervening constituent design cells is formed in accordance with a number of metrics profiling placements of the original constituent design cells of the design cell. The EDA tool is also provided with the ability to determine the metrics. In one embodiment, the metrics are weights reflective of at least edge placement activities associated with row/column coordinates of the design cell. Th EDA tool determines these weights associated with the row/column coordinates, and then uses the determined weights to select a subset of the row/column coordinates as cut line coordinates to logically partition the design cell into a number of regions.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: April 30, 2002
    Inventor: Laurence W. Grodd
  • Patent number: 6373713
    Abstract: The mechanism for inserting, extracting, sensing and locking a printed circuit board assembly (PCBA) in an electronic system provides both easier use and a longer service life for the PCBA as compared to a mechanism having two locking handles. Insertion, extraction, sensing and locking are simplified because a single handle can be used rather than two handles. The service life of the associated PCBA is extended because the forces applied to the PCBA are synchronous and applied more evenly than a PCBA having two handles, which reduces bending and other forces that can cause component failure.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: April 16, 2002
    Assignee: Oresis Communications
    Inventors: Chris J. Jensen, James D. Pileggi, Stanton A. Tellin
  • Patent number: 6367060
    Abstract: A clock tree synthesizer calculates balanced cluster sets of nodes a particular level of a clock tree in a circuit description based on a set of available buffer types. Each balanced cluster set is tested to see if it meets a design constraint. If the design constraint is not met for a particular balanced cluster set, the particular cluster set is removed from consideration in the clock tree solution. For the cluster sets that do meet the design constraint, a cost associated with each cluster set is calculated. A balanced cluster set that has the lowest cost is selected for the clock tree solution. In one embodiment, the lowest cost balanced cluster set for one level in the clock tree forms the nodes for the next higher level in the clock tree, and the process is repeated at each level of the clock tree up to a root node.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: April 2, 2002
    Inventors: C. K. Cheng, Liang-Jih Chao
  • Patent number: 6363503
    Abstract: A method and apparatus for processing and representing error messages within a computer-aided design environment is described. The present invention allows error/warning information to be stored in a central storage location by the function in which the error/warning causing fault occurs. The function then returns a result indicating that the function did not perform as expected. The calling function does not add an error/warning message of its own when returning, if necessary, to another calling function. Thus, only a single warning/error message can be stored and used for reporting the fault that caused the error/warning. In one embodiment, a hierarchical graphical error/warning log provides varying levels of error/warning information in response to user input.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: March 26, 2002
    Assignee: Autodesk, Inc.
    Inventors: James M. Clauss, Kevin M. Linscott, David J. Ford
  • Patent number: 6357040
    Abstract: Software is customized by generating, for a first set of software objects having usage characteristic data collected, a second set of software objects to totally or partially replace the first set of software objects. The second set of software objects is generated based at least in part on the collected usage characteristic data of the first set of software objects. In one embodiment, the generation includes optimizing the second set of software objects being generated based on the usage characteristic data, which include calling frequencies of caller/callee objects of the first set of software objects. In one embodiment, the generation is automatically performed at idle periods of the user's system, if the usage characteristics are determined to be sufficiently changed.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: March 12, 2002
    Assignee: Wildseed Limited
    Inventor: Swain W. Porter