Abstract: A computer system employing a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). The host processor core executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor core communicates with the emulation coprocessor core to cause the emulation coprocessor core to execute the foreign application program. Accordingly, application programs coded according to the foreign instruction set architecture can be executed directly in hardware. The computer system may be characterized as a heterogeneous multiprocessing system.

Abstract: An axially extended downhole seismic source is disclosed. In one embodiment, the seismic source includes multiple pressure storage chambers, each having an inlet valve and an outlet valve. The inlet valve is coupled between the pressure storage chamber and the interior of the drill string, and the outlet valve is similarly coupled between the pressure storage chamber and the annular space around the drill string. A compressible fluid may be provided in the pressure storage chambers, and pistons may be positioned to contact the compressible fluid. For each pressure storage chamber, an inlet piston contacts the compressible fluid and fluid inside the drill string, while an outlet piston contacts the compressible fluid and fluid in the annular space around the drill string. When the outlet valve is closed, the inlet valve can be opened to allow pressure inside the drill string to compress the compressible fluid inside the pressure storage chamber.

Abstract: An apparatus for preparing a plastic eyeglass lens includes a coating unit and a lens curing unit. The apparatus is preferably configured to allow the operation of both the coating unit and the lens curing unit. The apparatus may also include a post-cure unit and a controller. The controller is configured to control the operation of the coating unit, the lens curing unit and the post-cure unit. The lens forming unit may include an LCD filter disposed between activating light sources and a mold assembly. The mold assembly preferably includes two mold members held together by a gasket. The gasket preferably includes four protrusions spaced at 90 degree intervals about the gasket. A lens forming composition may include a first photochromic compound, a second photochromic compound and a light effector. The light effector may alter the color of a lens when exposed to photochromic activating light, when compared to a lens formed from a lens forming composition which does not include a light effector.

Abstract: Architecture, circuitry, and methods are provided for producing a content addressable memory (CAM). The CAM includes one or more CAM cells arranged in an array. Each CAM cell is symmetrical about its x- and y-axis to form rows and columns of the array. Additionally, each CAM cell can use either SRAM or DRAM storage cells implemented in either a binary or ternary arrangement. If the CAM cell is a ternary SRAM design, then the cell size is no more than 4 microns by 1-½ microns, assuming a 0.15 micron critical dimension. Critical dimension is noted as the smallest resolvable size for the particular process being employed. The CAM cell utilizes a selection circuitry that will disable the compare circuit during times when a compare operation is not being performed. This will ensure the compare circuit will not consume power during, for example, a read or write operation.

Abstract: A method for ordering electrofacies to assist in identification of mineral deposits is disclosed. Automated ordering of electrofacies allows geologists to draw inferences about the geological settings in which sediment deposit occurred without directly examining core samples or outcrops. The electrofacies order is determined by (a) training a one-dimensional linear self-organizing map to form an initial neural network that includes a plurality of neurons. The number of neurons is small in comparison to the number of electrofacies kernels (i.e., not greater than one-third the number of electrofacies kernels). (b1) A neuron is selected from the initial neural network. In the next step (b2), the processor determines if more than one electrofacies kernel is attached to the neuron. (b3) If more than one electrofacies kernel is attached to the neuron, then the neuron is split into the number of electrofacies kernels attached to the neuron.

Abstract: A system for supplying pigs to a subsea pig launcher using a system carried and controlled by a remotely operated vehicle. The pigs are carried in racks that hold multiple pigs. The racks are extended and the pigs are allowed to drop into the barrel of the subsea pig launcher. The system is also equipped with a system that retracts the racks if hydraulic and electrical power is lost during the reloading process so that the remotely operated vehicle can be retrieved to the surface safely. The reloading process can be carried out by a remotely operated vehicle support vessel without the need for heavy lifting equipment or a large deck area.

Abstract: A media meter mounts to a surface of a removable storage media or other product, and provides a visual indication of one or more parameters of the storage media or other product. The media meter includes circuitry that detects status signals transmitted by rf transmissions or directly connected by wires between an auxiliary memory device mounted on the storage media or product, or receives status signals via rf transmissions directly from the auxiliary memory. As another alternative, the media meter may be integrated with the auxiliary memory to receive status signals directly from the auxiliary memory. The status signals indicate the capacity of the storage media, the number of read and/or write errors that have occurred during back-up and retrieval, the number of times the storage media has been loaded with data or other information, and other dynamically-varying parameters.

Abstract: A signal analysis system and method for analyzing an input signal acquired from a mechanical system. The mechanical system may include at least one rotating apparatus. The signal analysis system may be configured to: (a) receive samples of the input signal, (b) perform an invertible joint time-frequency transform (e.g.

Abstract: This invention provides a process for producing hydrocarbons. The process involves contacting a feed stream comprising hydrogen and carbon monoxide with a catalyst in a reaction zone maintained at conversion-promoting conditions effective to produce an effluent stream comprising hydrocarbons, and uses a catalyst including (a) at least one catalytic metal for Fischer-Tropsch reactions (e.g., iron, cobalt, nickel and/or ruthenium) and (b) a non-layered mesoporous support which exhibits an X-ray diffraction after calcination that has at least one peak at a d-spacing of greater than 18 Ångstrom units.

Abstract: A method and system for displaying a series of video frames in reverse order. The video frames are received in groups of pictures (GOPs) from a storage medium. The method comprises steps of (a) decoding and storing a number of frames from an initial GOP into frame buffers according to an ordering of the frame buffers, (b) displaying the stored frames according to the reverse ordering of the frame buffers, (c) decoding and storing a number of frames from a first preceding GOP according to the reverse ordering of the frame buffers, (d) displaying the stored frames according to the ordering of the frame buffers, (e) decoding and storing a number of frames from a second preceding GOP according to the ordering of the frame buffers, and (f) repeating steps (b)-(e),for prior first and second preceding GOPs.

Abstract: A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. The microcode within the lock requesting node transmits a write command to write corresponding node identification data into a lock register in the arbitrating node. The lock requesting node iteratively reads the lock register until it finds its node identification data stored therein with a valid bit set. The lock requesting node then informs all remaining processing nodes to release shared system resources. This is accomplished through a release request bit and a release response bit in each processing node. After completion of lock operations, the lock requesting node sends a message to the arbitrating node to reset the valid bit in the lock register, and a broadcast message to each remaining node to reset the release request bit.

Abstract: Abstract A test executive program which provides greatly improved configurability and modularity, thus simplifying the creation, modification and execution of test sequences. The test executive program includes process models for improved flexibility, modularity and configurability. Process models provide a modular and configurable entity for encapsulating operations and functionality associated with a class of test sequences. The process model thus encapsulates a “testing process” for a plurality of test sequences. The process model enables the user to write different test sequences without repeating standard testing operations in each sequence. The test executive program also includes step types for improved configurability. A step type is a modular, identifiable unit configured by the user which defines common properties and/or operations associated with a plurality of steps.

Abstract: A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell.

Abstract: A processor has pre-cache and post-cache buffers. The pre-cache (or LS1) buffer stores memory operations which have not yet probed the data cache. The post-cache (or LS2) buffer stores the memory operations which have probed the data cache. As a memory operation probes the data cache, it is moved from the LS1 buffer to the LS2 buffer. Since misses and stores which have probed the data cache do not reside in the LS1 buffer, the scan logic for selecting memory operations from the LS1 buffer to probe the data cache may be simple and low latency, allowing for the load latency to the data cache for load hits to be relatively low. Furthermore, since the memory operations which have probed the data cache have been removed from the LS1 buffer, the simple scan logic may support high performance features such as allowing hits to proceed under misses, etc.

Abstract: A method for monitoring and measuring the buildup of deposits on the inner surface of a pipeline containing flowing fluid comprises (a) transmitting a first acoustic signal into the pipeline through the pipeline wall, (b) receiving echoes of the transmitted signal, and (c) determining from the received echoes how far from the pipeline inner surface the interface between the deposits and the flowing fluid lies. An alternative method for monitoring and measuring the buildup of deposits on the inner surface of a pipeline containing flowing fluid comprises (a) transmitting a first acoustic signal into the pipeline through the pipeline wall, (b) receiving echoes of the signal, and (c) using the Doppler frequency shift of the received echoes to determine how far from the pipeline inner surface the interface between the deposits and the flowing fluid lies.

Abstract: A processor employing a post-cache (LS2) buffer. Loads are stored into the LS2 buffer after probing the data cache. The load/store unit snoops the loads in the LS2 buffer against snoop requests received from an external bus. If a snoop invalidate request hits a load within the LS2 buffer and that load hit in the data cache during its initial probe, the load/store unit scans the LS2 buffer for older loads which are misses. If older load misses are detected, a synchronization indication is set for the load misses. Subsequently, one of the load misses completes and the load/store unit transmits a synchronization signal with the status for the load miss. The processor synchronizes to the instruction corresponding to the load miss, thereby discarding load hit which was subsequently snoop hit. The discarding instructions are refetched and reexecuted, thereby causing the load hit to reexecute subsequent to an earlier load miss.

Abstract: A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.

Abstract: A networking card has a plurality of pages for bearing at least one of a greeting or other message, a drawing and an object added to the networking card by successive recipients of the networking card. The networking card can be purchased by an initial sender. That person can add a message to a first page of the card and then send it to a first recipient. The first recipient in turn can add his or her own message to the networking card, for example on a second page of the networking card, and then send the card on to a second recipient. The process can be repeated until for example all of the pages have been used.

Abstract: A controller for a powered loudspeaker including a bus monitor configured to monitor a bus for activity and a click suppression unit coupled to the bus monitor and configured to control speaker volume by ramping the volume down if an absence of data on the bus is detected, and restoring the volume once bus activity begins again. In this manner, undesired clicks and hisses upon power up and power down are minimized.

Abstract: A system and method is described for safely and economically providing up to 1800 watts to downhole equipment over existing logging cables. In one embodiment, the system includes a standard multiconductor logging cable which supports orthogonal signal transmission modes on circumferentially spaced insulated conductors. A high-power power source on the surface is coupled to the insulated conductors in the cable to drive a power signal on the lowest impedance signal transmission mode. Bearing in mind that high-power electrical currents can present a safety hazard, system safety may be enhanced by the addition of a reliable current imbalance detector configured to shut down all power sources when currents in the insulated conductors don't add up to zero. The system may further include multiple power sources operating on different independent signal transmission modes, and may also include multiple telemetry channels which share the power transmission modes via frequency multiplexing.