Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.

Abstract: A static bi-stable mechanical latch comprises a latch member pivotally mounted to a frame and rotatable between an opened-position stop and a closed-position stop. The latch member includes a first arm having a hooked end and a magnetic mass mounted thereon, and a second arm having a latch coil and a soft magnetic mass mounted thereon. The second arm is also provided with a tang or bump. The actuator is provided with an angular protuberance and a tip which is captured by the hooked end of the latch member when the actuator arm is positioned so that the head is in the landing zone and the latch member is in the closed position. The pivot point of the latch member is positioned so the angular protuberance of the actuator arm engages the tang or bump when the actuator is moving towards the landing zone and is in a preselected position close to or in the landing zone.

Abstract: An adaptive photoreceptor semiconductor circuit for long-time-constant continuous learning having a low offset and insensitivity to light includes a photodiode in series with an MOS feedback transistor connected across a potential difference. An inverting amplifier comprises a first MOS amplifier transistor having its gate connected to a source of bias voltage potential in series with an cascode transistor having its gate connected to a source of cascode voltage potential and a second MOS amplifier transistor having its gate connected to the common connection between the photodiode and the MOS feedback transistor. An output node comprises the connection between the first MOS amplifier transistor and the cascode transistor. A light insensitive adaptive element has a driven node connected to the output node and an isolated node connected to the gate of the MOS feedback transistor. A capacitive voltage divider is connected between a first power supply rail, the adaptive element, and the output node.

Abstract: A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

Abstract: A method for simultaneously programming a plurality of antifuses each having a first electrode connected to a common node and each having a second electrode connected to an isolated node electrically isolated from the nodes of each of the other antifuses includes the steps of precharging the common node and the isolated nodes to an intermediate voltage potential selected to minimize the stress on all antifuses; precharging the isolated nodes of selected ones of the antifuses to a first programming voltage potential placing a second programming voltage potential on said common node, the first and second programming voltage potentials selected such that the difference between them is sufficient to cause programming of said antifuses and such that said intermediate potential is substantially centered between them, waiting a predetermined amount of time; and measuring the current flowing between the common node isolated nodes.

Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures.A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Abstract: A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled.

Abstract: An integrated circuit having a plurality of input/output modules, each of which has input/output modules including an input module section having an input node connected to a unique input/output pin on the integrated circuit and an output node communicating with a unique first internal node in the integrated circuit, and an output module section having an input node communicating with a unique second internal node in the integrated circuit and an output node communicating with the unique input/output pin. Each input/output module is programmable by a user such that its function may be defined as an input module, an output module, or a bi-directional module. The integrated circuit further has two states, a first unprogrammed state where none of the functions of the input/output modules have been defined, and a second, programmed state in which the functions of the input/output modules have been defined by either enabling or disabling the output section of the input/output module.

Abstract: The present invention relates to a fishing system in which one end of a fishing line is attached to a remotely controlled miniature boat powered by two propellers and controllable from a control point. The boat is connected to the control point by a fishing line as well as by a control link. At the rear end of the boat a rigidly mounted tail extends from the boat to provide a point for the attachment of the fishing line at or near the water's surface and clear of the propellers. A plurality of separate lines having hooks may be attached to the fishing line with hangers. A plurality of horizontally dispersed hooks may thus be set to catch fish over a wide area.

Abstract: A method for changing the shape of the cornea of an eye to correct refractive disorders comprises employing laser radiation having a selected wavelength, beam pattern, and beam power profile, and employing this radiation for a selected time duration, wherein the wavelength, beam pattern, beam power profile and time duration are chosen to selectively kill or injure keratocytes and to avoid shrinking the collagen in a selected treatment volume of the cornea which has a posterior boundary which is at least 10% of the total stromal depth, and preferably between 50-90% of the stromal depth.

Abstract: The invention provides an electrophoresis system which separates charged chemical substances by means of applying an electrical potential across a buffer solution which includes those chemical substances. The system of the invention includes a power supply and control system which has a wide dynamic range of constant voltage, current and power which may be supplied, and is therefore particularly suited to the needs of the electrophoresis system. In the invention, the power supply includes a flyback topology and a control system which allows an operator to specify a wide range of constant voltage, current or power supply requirements for the electrophoresis system.

Abstract: An isolation conductor is provided between a first conductor and a plurality of second conductors to which potential connections can be made from the first conductor. An isolation antifuse is connected between the first conductor and the isolation conductor. Individual antifuses are connected between the isolation bus and each of the plurality of second conductors. A pull-down or pullup transistor is connected between the isolation conductor and a selected circuit node to allow programming of the isolation antifuse and an isolation transistor may be connected between the first conductor and the isolation conductor to allow testing of the isolation conductor.

Abstract: A method for isolating a first low-voltage circuit node comprising an output of a low-voltage device from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes the step of raising the normal power supply voltage provided to the low-voltage devices to an intermediate level lower than the programming voltage but high enough to protect the outputs of the low voltage devices from damage. The output to be protected is caused to assume a desired state and is then inhibited from changing state during the programming cycle. Programming voltage is then applied to the low voltage circuit node.

Abstract: A first passive ESD protection device for an electronic component in a microcircuit includes a fuse element shunting the component to be protected and includes a passive programming path from the outside of the microcircuit to the fuse element. A second passive ESD protection device is deactivatable and reactivatable and includes a first fuse element shunted by a second fuse element in series with a first antifuse element. Shunting the second fuse element with a third fuse element in series with a second antifuse element permits a second deactivation and reactivation to be performed. Additional deactivation/reactivation cycles may be permitted by providing additional series combinations of fuse elements and antifuse elements shunting the preceding fuse element. Combinations of the passive protection device and dual elements comprise ESD protection schemes which may be deactivated and activated multiple times.

Abstract: In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with the first conductor, and a plurality of antifuses connected between the first conductor and the second conductors at the intersections, a method for testing the integrity of the plurality of antifuses after attempting to program a selected one of the antifuses, including the steps of precharging each of the second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of the second conductors; placing a second voltage potential on the first conductor, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of the second conductors.

Abstract: An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array.

Abstract: A division-of-amplitude photopolarimeter based on conical grating diffraction includes a diffraction grating and at least four photodetectors. An incident light beam is directed at the grating at an oblique incidence angle .PHI. and the grating grooves are inclined at an arbitrary angle .alpha. with respect to the plane of incidence. Each of the photodetectors is positioned to intercept one of the diffracted orders and may be an area array detector if spectropolarimetry use is desired. Polarizing means may be inserted in the paths of one or more of the diffracted orders. A division-of-amplitude photopolarimeter based on planar grating diffraction includes a diffraction grating and at least four photodetectors; the grating is placed in the conventional spectrometer orientation with its grating grooves perpendicular to the plane of incidence.

Abstract: Apparatus for preventing data corruption on a disk due to mechanical shock occurring during the write process to the disk includes a mechanical shock sensor to sense mechanical shocks having a magnitude exceeding a predetermined threshold. Write disable circuitry responsive to the mechanical shock sensor interrupts the write current to the disk drive write head. Repositioning circuitry then repositions the data head over the original data track and the incomplete data that was interrupted by the mechanical shock is rewritten.

Abstract: A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line.