Abstract: An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. A processor operating under program control with the program has the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. A first mask signal is set to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer. Otherwise, the first mask signal is set to have 8 lower bits in an ON position.

Abstract: An analog-to-digital converter comprises a modulator connected to an analog input signal, a decimator connected to the output of the modulator, a normalizer connected to the output of the modulator and forming a digital output signal, and a programmable gain control circuit connected to the output of the normalizer and providing feedback gain control to the modulator and the decimator.

Abstract: A spring clip having opposed teeth is attached to a lanyard. The lanyard may be worn around a user's neck. The spring clip with opposing teeth fits around and securely grasps the seal ring at the top of a conventional pressurized spray bottle. Alternatively, a spring band fits around the seal ring of a conventional pressurized spray bottle. A lanyard attached to the spring band allows the bottle to be hung from a user's neck or other part of the body for ease of access and use. In a third aspect, a band having a high friction or adhesive inner surface is applied to the main body of a conventional cylindrical pressurized spray bottle. A lanyard attached to the band allows the bottle to be hung from a part of the user's body as before.

Abstract: According to the present invention, a secured memory comprises a first level security zone having an access code controlling access to the secured memory prior to an issuer fuse being blown, a security code attempts counter preventing access to the secured memory when a predetermined number of attempts at matching the access code have been made prior to resetting the security code attempts counter, a plurality of application zones, each of the plurality of application zones comprising: a storage memory zone, an application security zone having an application zone access code controlling access to the storage memory zone after an issuer fuse has been blown, an application zone security code attempts counter preventing access to the application zone when a predetermined number of attempts at matching the application zone access code have been made prior to resetting the application zone security code attempts counter, an erase key partition having an erase key code controlling erase access to the storage memory

Abstract: Hot-electron injection driven by a hole impact ionization mechanism at the channel-drain junction provides a new method of hot electron injection. Using this mechanism, a four-terminal pFET floating-gate silicon MOS transistor for analog learning applications provides nonvolatile memory storage. Electron tunneling permits bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. The synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. Synaptic arrays employing these devices enjoy write and erase isolation between array synapses is better than 0.01% because the tunneling and injection processes are exponential in the transistor terminal voltages.

Abstract: An antifuse comprises an antifuse material disposed between a lower conductive electrode and an upper conductive electrode. The antifuse material comprises a layer of amorphous silicon disposed between two layers of silicon nitride. A thin layer of silicon dioxide is disposed between the layer of amorphous silicon and one of the silicon nitride layers.

Abstract: An autozeroing floating-gate amplifier (AFGA) is an integrated continuous-time filter that is intrinsically autozeroing. It can achieve a highpass characteristic at frequencies well below 1 Hz. In contrast with conventional autozeroing amplifiers that eliminate their input offset, the AFGA nulls its output offset. The AFGA is a continuous-time filter; it does not require any clocking. The AFGA includes at least one floating-gate MOS transistor that is capable of hot-electron injection of electrons onto the floating gate of the MOS transistor. Electrons are continuously removed from the floating gate(s), for example, via Fowler-Nordheim tunneling. The AFGA has a stable equilibrium for which this tunneling current is balanced by an injection current of equal magnitude.

Abstract: An enhanced multimedia device driver for personal computers includes a polling process which performs polling of the hardware devices. The device driver creates a helper thread for each hardware device which executes in the client context. Each polling process wakes up at a regular interval at which time it polls the status register of the corresponding hardware device. If there is an event pending at the status register, then the polling process signals the event pending to all of the helper threads. Each helper thread wakes up and checks the reason for the wakeup. At this point, the helper thread will initiate a data transfer using programmed I/O if called for by the reason for the wakeup. Through the use of the present invention, the DMA controller, the system interrupt controller, and the kernel interrupt handler of the kernel are not employed in data transfers and the use of DMAs and/or IRQs for data transfers is eliminated.

Abstract: A package having a container having an inner surface, an outer surface, and a sidewall defining a cavity, with the container having an inner locking tab in the cavity defining a recess in the outer surface of the container, and with a stiffening material being placed in the recess to add strength to the locking tab.

Abstract: A media independent interface (MII) is utilized on each processor card of a multi-processor card system in a carrier sense multiple access/collision detection (CSMA/CD) standard bus configuration to provide a data communications bus. This permits standard Media Access Control (MAC) devices to be used with the MII. The collision domain is implemented by having each active processor card using the data communications bus assert an analog signal on a single conductor of the back plane and sense its voltage value to determine if one or more processor cards are currently accessing the bus.

Abstract: The invention is an apparatus and method for receiving a message having a first format and for converting the message from the first format to a second format that is compatible for reception by a messaging interface having a destination address corresponding to an intended recipient. In the preferred embodiment, a computer system is used to receive and send messages between messaging interfaces and networks which may be dissimilar from each other. A variety of network interfaces is used to communicate with the networks and which may optionally have a first interface and a second interface for interfacing to a first and second network, respectively. The messages may optionally be presented through a web page. A forwarding program or equivalent may be used to forward subscriber messages to or from remote locations served by a remote computer system, enabling a messaging user to use the remote computer system as a local access point.

Abstract: A number of adder structures (also referred to herein as "tiles" and "Quickadders.TM.") are provided which may be constructed with positively and/or negatively weighted and signed inputs and outputs and which may be placed so as to span one or more bitslices of a multiplier array. In a second aspect of the present invention, groups of replicable circuitry columns are provided for forming multiplier arrays for multiplying binary numbers X and Y to obtain a binary product Z. These groups of columns of circuitry include left column groups to handle X-inputs to the array, internal column groups, and right column groups to handle outputs to a CLA adder/subtractor (or equivalent) for processing the MSBs of the product. The LSBs of the product are produced directly by the array. The groups may be thought of as replacing 2, 3 or 4 conventional columns of full-adder circuitry of a basic array such as that shown in FIGS. 1 and 2.

Abstract: In a double-sided pulse width modulator, an amplifier has a first input connected to a first reference potential, a second input, and an output. A first bank of storage elements have a first terminal connected to the second input of the amplifier, and a second terminal. A first bank of switches have an output terminal connected to a second terminal of the storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of the modulator and a polarity control bit for a first value to be input into the input terminals. A feedback storage element is connected in parallel with a first timing switch between the second input of the amplifier and the output of the amplifier. A comparator has a first input connected to a second reference potential, a second input, a timing enable input, and an output. A second bank of storage elements have a first terminal connected to the second input of the comparator, and a second terminal.

Abstract: A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having a substantially aluminum-free conductive link. The substantially aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness.

Abstract: A hybrid integrate circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits.

Abstract: In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit mask; performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits. Further, an apparatus for parallel processing a signed value to form an absolute value comprises: means for performing an arithmetic shift right of N-1 bit to form a bit mask; means for performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and means for subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits.

Abstract: The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter.

Abstract: A safe external A/C adapter protecting the user against hazardous, high-voltage D/C output. High voltage is defined as any voltage in excess of 60V D/C. The adapter provides an internal remote ON/OFF circuit that automatically switches the D/C output OFF unless the output plug is seated within a mating socket disposed in an electronic device powered by the adapter. When the output plug is so seated, the hazardous voltage output is inaccessible to the user. In addition, a secondary shutdown circuit is provided that latches off the A/C input in the unlikely event that the remote ON/OFF circuit should fail. The secondary shutdown circuit is largely independent from the primary remote ON/OFF circuit, and can be implemented using control circuitry already present in the adapter. No special mechanical connectors are required.

Abstract: In a first aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a test probe circuit associated with a column in the array, selecting at least one logic module associated with the test probe circuit, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.

Abstract: A capacitive touch pad comprises a substrate material, such as a PC board type laminate material, having a plurality of first parallel conductive traces running in a first (X) direction disposed on a first face thereof, and a plurality of second parallel conductive traces running in a second (Y) direction, usually orthogonal to the first direction, disposed on an opposed second face thereof. A layer of pressure-conductive material is disposed over one of the faces of the substrate. A protective layer with a conductive coating on its back surface is disposed over the top surface of the pressure-conductive material to protect it. In an alternate embodiment, a capacitive touch sensor comprises a rigid substrate material having a conducting material disposed on one face thereof. A layer of pressure-conductive material is disposed over the conductive material on the substrate.