Abstract: A QoS monitoring system and method for a DiffServ-capable network element operable in a trusted domain network such as an ISP network. The network element is organized as a plurality of terminating line cards interconnected via a switch fabric capable of supporting virtual ingress/egress pipes (VIEPs). Buffer queues on the ingress and egress sides of the network element, which are established for supporting traffic flows on individual VIEPs, are monitored for determining QoS parametric information such as throughput, loss, delay, jitter and available bandwidth. A policing structure is operably coupled with a buffer acceptance and flow control module for monitoring traffic behavior on the ingress side. Another buffer acceptance/flow control module and aggregate-level monitoring module are disposed on the egress side of the network element that cooperates with a scheduler which shapes outgoing traffic.

Abstract: The lock cylinder assembly of the present invention incorporates a number of features designed to defeat attempts to pick or destroy the lock. The lock cylinder assembly employs multiple arrays of pass key pins, making picking of the lock much more difficult. Second, the arrangement of the pass key pins in separate arrays requires that multiple cuts would have to be made into the lock housing mogul or cylinder blank in order to defeat the lock cylinder assembly. Third, the lock cylinder assembly of the present invention may incorporate multiple sets of hardened dowel pins to prevent drilling through the lock housing mogul in the area of the driver pins. Fourth, the lock cylinder assembly of the present invention may incorporate a hardened cylinder shield behind the front face of the cylinder blank to prevent drilling through the cylinder blank.

Abstract: A system and method for optimizing the use of packet-resources by releasing a hanging packet-data connection when a Mobile Station (MS) performs a power-down while involved in a dormant packet-data session. A Base Station Controller (BSC) sends a message to a Mobile Switching Center (MSC) indicating that the MS has powered down. The MSC determines that the packet-data session is dormant, and sends an instruction to the BSC in a class-0 connectionless transaction to release network resources associated with the packet-data session. The BSC then sends an instruction to a Packet Control Function (PCF) to tear down the associated resources, and the packet-data connection is released by a Packet Data Service Node (PDSN) in response to the tearing down of the resources by the PCF.

Abstract: A hierarchically organized, compilable semiconductor memory circuit having multiple levels with simultaneous access and cache loading. A first level memory portion and at least a next level memory portion are provided as part of the semiconductor memory circuit, wherein the memory portions are associated with separate Data In (DIN) and Data Out (DOUT) buffer blocks for effectuating data operations. DIN buffer blocks of the first level and intermediate levels, if any, are provided with multiplexing circuitry that is selectively actuatable for providing data accessed in the next level memory portion to Local Data In (LDIN) driver circuitry, whereby the accessed data is simultaneously loaded into the first and intermediate levels. Accordingly, extra clock cycles are saved from cache loading of the data used for subsequent memory operations.

Abstract: A garden cart handle having a main shank having a principal axis, a first end pivotably connectable to a garden cart and a second end opposite the first end. A handgrip portion is connected to the second end of the main shank, having a principal axis disposed substantially orthogonal to the principal axis of the main shank, a first end and a second end. A hinged portion, having an inboard end and an outboard end, is connected to the handgrip portion through a pivoting connection so as to allow the hinged portion to pivot about the principal axis of the handgrip portion. A flange is disposed on the outboard end of the hinged portion, shaped and sized to connect to a trailer tongue of a tractor. A latch is disposed on the second end of the main shank, shaped and sized to secure the hinged portion against pivoting.

Abstract: A system and method in a packet-switched radio access network of sending data packets over a radio interface from a Mobile Station (MS) to a Radio Network Controller (RNC) using multiple data transmission paths. When the MS launches a new application through a first base station (BS1), a Multi-path Context Activator (MCA) in the RNC determines whether the bandwidth required by the new application exceeds the bandwidth capacity of the radio interface portion of the first data transmission path. If so, the RNC identifies a second BS (BS2) that has the capacity to provide a portion of the radio interface bandwidth required. The MS then transmits separate data streams to BS1 and BS2 as over the radio interface. The MCA combines the separate upstream data portions. For downstream packets, the MCA separates the packets into two streams which are sent to an MCA in the MS via BS1 and BS2.

Abstract: An apparatus and method for manufacture and testing of semiconductor chips (14) is disclosed. The invention comprises the use of an interposer (22) having a plurality of electrical contact pads (26) on each surface connected by a plurality of conductors (32, 34). After assembly of the interposer (22) to a semiconductor wafer (12), the wafer-interposer assembly (10) is attached to a testing unit (46) wherein the semiconductor chips (14) on the wafer (12) are tested. After testing, the interposer-wafer assembly (10) is singulated into a plurality of chip assemblies (62), each chip assembly (62) comprising a silicon chip (64) and the permanently attached interposer (66).

Abstract: A matched set of integrated circuit chips (24) and a method for assembling such integrated circuit chips (24) into a matched set are disclosed. A semiconductor wafer (18) having a plurality of integrated circuit chips (24) is electrically and mechanically coupled to a wafer interposer (12) to form a wafer-interposer assembly (10). The integrated circuit chips (24) of the wafer (18) are then tested together by attaching the wafer-interposer assembly (10) to a testing apparatus and running the integrated circuit chips (24) through various testing sequences. The wafer-interposer assembly (10) is then diced into a plurality of chip assemblies each having a chip (24) and a section of the wafer interposer (12). Based upon the testing, the chip assemblies are sorted and at least two of the chip assemblies are selected for inclusion in the matched set.

Abstract: The present invention provides a wafer-interposer assembly apparatus and method. The method for manufacturing the wafer-interposer assembly including the steps of providing a semiconductor wafer and an interposer. The semiconductor wafer including one or more semiconductor die, each semiconductor die having one or more first electrical contact pads. The interposer having one or more communication interfaces and a second electrical contact pad corresponding to each of the one or more first electrical contact pads on each semiconductor die of the semiconductor wafer, and at least one of the second electrical contact pads electrically connected to the one or more communication interfaces. The wafer-interposer assembly is formed by connecting each first electrical contact pad of the semiconductor wafer to the corresponding second electrical contact pad of the interposer with a conductive attachment element.

Abstract: Employee Internet usage is monitored to identify the web sites employees visit and the amount of time employees spend at each site. The system utilizes a client-based module which monitors Internet access, which operates in conjunction with an enforcement supervisor located on a remote web server. A client-based monitoring module performs all of the monitoring and logging activity. The previous web page title, location (URL) and time spent are stored by the client component in memory on the client computer. The web page title and URL are obtained from system notifications from the browser to the client component. The client computer uploads the log containing the web page information to a web-based supervising module.

Abstract: A system and method for setting up a multi-party conference call in a packet-switched radio telecommunications network in which a Gatekeeper (GK) has established an on-going two-party call between a first party and a second party. The first party sends an enhanced Facility message to the GK that indicates a multi-party conference call is desired, and includes a globally unique conference identity and a list of telephone numbers for third parties to be joined. A Multipoint Controller (MC) provides an Internet Protocol (IP) address of a Multipoint Processor (MP) to each of the parties, and provides the IP addresses of the parties to the MP. The MC then negotiates media sessions with each of the parties, and sends the negotiation results to the MP. Each of the parties then sends its media payload to the MP where the payloads are mixed and forwarded to the other parties.

Abstract: Matrix recovery and link maintenance for a signaling node in an SS7 network. The signaling node comprises a planar redundant switching matrix with master and standby sides. End devices for trunk interfacing and channel data control receive data and timing from the master side, de-coupled from data and timing paths of the standby side. In steady-state, revenue traffic between the SS7 network and the signaling node runs on the master side in a pulse code modulated (PCM) form. Test channels are set up on both sides. Test patterns are propagated on the test channels for monitoring failures of timing path, PCM data, and device communication. When a failure condition is detected on the master side, the signaling node transmits idle signaling to the network, so that the revenue traffic is suspended and the link is maintained in an in-service state.

Abstract: A matched set of integrated circuit chips (34, 38) includes a chip (34) from a first wafer (22) and a chip (38) from a second wafer (24). The chips (34, 38) of the first and second wafers (22, 24) are tested together as part of a wafer-interposer assembly (10). The matched set comprises a first chip assembly diced from the wafer-interposer assembly (10) having one of the chips (34) from the first wafer (22) and a second chip assembly diced from the wafer-interposer assembly (10) having one of the chips (38) from the second wafer (24). A substrate is electrically coupled to the first and second chip assemblies, the first and second chip assemblies being selected for the matched set based upon sorting of the chips (34, 38) of the first and second wafers (22, 24) as a result of the testing.

Abstract: A distributed telecommunications switching subsystem (100) receives and distributes data packets passed between a plurality of switching subsystems or channel banks (102, 104, 106) and a data packet switch (110). Each channel bank (102) has a stored list of addresses. When a channel bank (102) receives a data packet, it compares the address of the data packet to its stored list of addresses, and transmits the data packet to another channel bank (104) if the address of the data packet does not correspond to any of the addresses in its stored list of addresses. The data packet is passed on until it reaches a channel bank (106) with a matching address or else it is appropriately handled by a last channel bank (106) in the chain. If the address of data packet matches an address in its stored list of addresses, the channel bank (102) passes the data packet through a subscriber interface card (120) to a customer premises equipment unit (108) corresponding to the address of the data packet.

Abstract: A system and method for providing high voltage resistance capability in a receptacle apparatus for accepting a high-density compliant pin connector. A plurality of high-density compliant pin through-holes are formed in a printed circuit board for receiving the pins of the high-density compliant pin connector. The through-holes are plated using an electrically conductive material, whereby conductive pads are formed around the plated through-holes on at least one side of the printed circuit board. Thereafter, the conductive pads around the plated through-holes on the printed circuit board are removed by controlled depth back-drilling so as to increase the inter-pad clearance of the through-holes for withstanding foreign voltages.

Abstract: A static memory cell having reduced susceptibility to soft error events, wherein data storage nodes are hardened by way of junction isolation. The memory cell is comprised of a pair of cross-coupled inverters. A first inverter is formed with a first N-channel Metal Oxide Semiconductor (NMOS) device and a first P-channel MOS (PMOS) device, with a first isolation device disposed therebetween. A second inverter is cross-coupled to the first inverter to form a pair of data storage nodes therein. The second inverter is also provided with a second isolation device disposed between its pair of NMOS and PMOS devices. A first data storage node is formed at a coupling between the first PMOS device and the first isolation device and a second data storage node is formed at a coupling between the second PMOS device and the second isolation device.