Abstract: A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

Abstract: A circuit includes a micro electro mechanical switch and a detection circuit. The micro electro mechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact in response to an electrostatic force provided by a top activation electrode and a bottom activation electrode. The detection circuit is electrically coupled to the top and bottom activation electrodes and is for detecting a first capacitance value between the top and bottom activation electrodes when the movable portion is in a first position and for detecting a second capacitance value when the movable portion is in a second position. By detecting a change in the capacitance, it can be determined if the switch is open or closed.

Abstract: A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Abstract: A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Abstract: A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.

Abstract: An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Abstract: A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device. The capacitor has a lower plate electrode and an upper plate electrode. An insulator is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer is deposited over the metal of an interconnect layer. The first insulating layer is planarized using a chemical mechanical polish (CMP) process. A second insulating layer is then deposited over the planarized first insulating layer. The first plate electrode is formed over the second insulating layer. An insulator is formed over the first plate electrode and functions as the capacitor dielectric. A second plate electrode is formed over the insulator. Planarizing the first insulating layer and depositing a second insulating layer over the first insulating layer, reduces defects and produces a more reliable capacitor.

Abstract: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

Abstract: A method for forming a portion of a semiconductor device includes: patterning gate stack layers overlying a substrate into a gate stack; implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the gate stack; oxidizing the gate stack at first oxidation conditions to form an oxidation layer on sidewalls of the gate stack; and oxidizing the gate stack at second oxidation conditions to form further oxidation of the oxidation layer on sidewalls of the gate stack. The second oxidation conditions are different from the first oxidation conditions.

Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).

Abstract: A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled to the first line of memory cells; and a second power supply line coupled to the second line of memory cells. For the case where the second line of memory cells is selected for writing, a switching circuit couples the power supply terminal to the first power supply line, decouples the first power supply line from the second line of memory cells, and couples the second power supply line to the first capacitance structure. The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure. This provides more margin in the write operation on a cell in the selected line of memory cells.

Abstract: An analog filter (10) having a bandwidth tracking circuit includes an analog filter element (14) and a digital tracking loop (22). The digital tracking loop (22) compares a magnitude difference to a predetermined threshold to generate an error signal. The magnitude difference is determined during a closed loop bandwidth calibration by subtracting a first magnitude of an analog input signal over a predetermined frequency range to a second magnitude of the analog input signal over the predetermined frequency range located near the bandwidth frequency. Use of the digital tracking loop (22) provides a digital approach for achieving bandwidth tracking of an analog filter without the need for achieving any manufacturing process matching between the analog filter and the tracking circuit itself. The analog filter element (14) may be either a lowpass, highpass, bandpass, active or passive filter element.

Abstract: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes, for example, a plurality of parallel-connected transistors (112) coupled between the array (12) of non-volatile memory cells and a power supply terminal.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: A noise blanker (40, 106) monitors and removes noise from a sampled signal by adaptive filtering (98, 150) the sampled signal to generate trained adaptive filter prediction coefficients. The sampled signal is provided as an output signal when the noise blanker is in a training mode. A noise monitor (34, 154) detects whether noise contained within the sampled signal exceeds a predetermined threshold and provides a control signal in response to the detecting. The noise blanker is placed in a prediction mode for a predetermined amount of time in response to asserting the control signal. A prediction output signal is generated using a plurality of prediction coefficients as an all-pole filter. The prediction output signal has minimal noise content.